| Message ID | 20220318103729.157574-21-Julia.Lawall@inria.fr (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 339ac71b233ee9ab5036be3abca0e5df793b5f64 |
| Headers | show |
| Series | ARM: spear: fix typos in comments | expand |
Hello: This patch was applied to soc/soc.git (for-next) by Arnd Bergmann <arnd@arndb.de>: On Fri, 18 Mar 2022 11:37:16 +0100 you wrote: > Various spelling mistakes in comments. > Detected with the help of Coccinelle. > > Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> > > --- > arch/arm/mach-spear/spear13xx.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Here is the summary with links: - ARM: spear: fix typos in comments https://git.kernel.org/soc/soc/c/339ac71b233e You are awesome, thank you!
On 18-03-22, 11:37, Julia Lawall wrote: > Various spelling mistakes in comments. > Detected with the help of Coccinelle. > > Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> > > --- > arch/arm/mach-spear/spear13xx.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c > index 74d1ca2a529a..b38391e9d8bf 100644 > --- a/arch/arm/mach-spear/spear13xx.c > +++ b/arch/arm/mach-spear/spear13xx.c > @@ -29,7 +29,7 @@ void __init spear13xx_l2x0_init(void) > /* > * 512KB (64KB/way), 8-way associativity, parity supported > * > - * FIXME: 9th bit, of Auxillary Controller register must be set > + * FIXME: 9th bit, of Auxiliary Controller register must be set > * for some spear13xx devices for stable L2 operation. > * > * Enable Early BRESP, L2 prefetch for Instruction and Data, Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c index 74d1ca2a529a..b38391e9d8bf 100644 --- a/arch/arm/mach-spear/spear13xx.c +++ b/arch/arm/mach-spear/spear13xx.c @@ -29,7 +29,7 @@ void __init spear13xx_l2x0_init(void) /* * 512KB (64KB/way), 8-way associativity, parity supported * - * FIXME: 9th bit, of Auxillary Controller register must be set + * FIXME: 9th bit, of Auxiliary Controller register must be set * for some spear13xx devices for stable L2 operation. * * Enable Early BRESP, L2 prefetch for Instruction and Data,
Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> --- arch/arm/mach-spear/spear13xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)