| Message ID | 20220407105835.10962-3-kavyasree.kotagiri@microchip.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | ARM: dts: Add LAN966x QSPI nodes | expand |
On 07/04/2022 12:58, Kavyasree Kotagiri wrote: > Enable QSPI0 controller and sst26vf016b SPI-NOR flash present on it. > > Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > --- > arch/arm/boot/dts/lan966x-pcb8291.dts | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts > index 3281af90ac6d..99d96d46661d 100644 > --- a/arch/arm/boot/dts/lan966x-pcb8291.dts > +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts > @@ -62,3 +62,18 @@ > &watchdog { > status = "okay"; > }; > + > +&qspi0 { > + status = "okay"; > + > + spi-flash@0 { Just "flash" please (to be generic). > + compatible = "jedec,spi-nor"; > + reg = <0>; > + spi-max-frequency = <20000000>; > + #address-cells = <1>; > + #size-cells = <1>; Why do you need address/size cells here? You don't have any children. > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > + m25p,fast-read; > + }; > +}; Best regards, Krzysztof
On 4/7/22 13:58, Kavyasree Kotagiri wrote: > Enable QSPI0 controller and sst26vf016b SPI-NOR flash present on it. > > Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > --- > arch/arm/boot/dts/lan966x-pcb8291.dts | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts > index 3281af90ac6d..99d96d46661d 100644 > --- a/arch/arm/boot/dts/lan966x-pcb8291.dts > +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts > @@ -62,3 +62,18 @@ > &watchdog { > status = "okay"; > }; > + > +&qspi0 { > + status = "okay"; > + > + spi-flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0>; > + spi-max-frequency = <20000000>; You should describe the flash's maximum frequency: • High-Speed Clock Frequency: - 2.7V-3.6V: 104 MHz maximum - 2.3V-3.6V: 80 MHz maximum https://ww1.microchip.com/downloads/aemDocuments/documents/MPD/ProductDocuments/DataSheets/SST26VF016B-2.5V-3.0V-16-Mbit-Serial-Quad-IO-%28SQI%29-Flash-Memory-20005262G.pdf > + #address-cells = <1>; > + #size-cells = <1>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > + m25p,fast-read; > + }; > +};
diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts index 3281af90ac6d..99d96d46661d 100644 --- a/arch/arm/boot/dts/lan966x-pcb8291.dts +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts @@ -62,3 +62,18 @@ &watchdog { status = "okay"; }; + +&qspi0 { + status = "okay"; + + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + }; +};
Enable QSPI0 controller and sst26vf016b SPI-NOR flash present on it. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> --- arch/arm/boot/dts/lan966x-pcb8291.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+)