diff mbox series

[v4] ARM: dts: lan966x: add support for pcb8290

Message ID 20220825065135.1075049-1-horatiu.vultur@microchip.com (mailing list archive)
State Not Applicable
Headers show
Series [v4] ARM: dts: lan966x: add support for pcb8290 | expand

Commit Message

Horatiu Vultur Aug. 25, 2022, 6:51 a.m. UTC 
Add basic support for pcb8290. It has 2 lan8814 phys(each phy is a
quad-port) on the external MDIO bus and no SFP ports.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
---
v3->v4:
- add missing Copyright to dts file

v2->v3:
- update coma-mode-gpios, set them to OPEN_DRAIN

v1->v2:
- add comments for pps_out_pins and ptp_ext_pins pins
- fix commit message.
---
 arch/arm/boot/dts/Makefile            |   1 +
 arch/arm/boot/dts/lan966x-pcb8290.dts | 175 ++++++++++++++++++++++++++
 2 files changed, 176 insertions(+)
 create mode 100644 arch/arm/boot/dts/lan966x-pcb8290.dts

Comments

Claudiu Beznea Aug. 31, 2022, 7:43 a.m. UTC | #1 
On 25.08.2022 09:51, Horatiu Vultur wrote:
> Add basic support for pcb8290. It has 2 lan8814 phys(each phy is a
> quad-port) on the external MDIO bus and no SFP ports.
> 
> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>

Applied to at91-dt, thanks!

> ---
> v3->v4:
> - add missing Copyright to dts file
> 
> v2->v3:
> - update coma-mode-gpios, set them to OPEN_DRAIN
> 
> v1->v2:
> - add comments for pps_out_pins and ptp_ext_pins pins
> - fix commit message.
> ---
>  arch/arm/boot/dts/Makefile            |   1 +
>  arch/arm/boot/dts/lan966x-pcb8290.dts | 175 ++++++++++++++++++++++++++
>  2 files changed, 176 insertions(+)
>  create mode 100644 arch/arm/boot/dts/lan966x-pcb8290.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 05d8aef6e5d2..595e870750cd 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -788,6 +788,7 @@ dtb-$(CONFIG_SOC_IMXRT) += \
>  dtb-$(CONFIG_SOC_LAN966) += \
>  	lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \
>  	lan966x-kontron-kswitch-d10-mmt-8g.dtb \
> +	lan966x-pcb8290.dtb \
>  	lan966x-pcb8291.dtb \
>  	lan966x-pcb8309.dtb
>  dtb-$(CONFIG_SOC_LS1021A) += \
> diff --git a/arch/arm/boot/dts/lan966x-pcb8290.dts b/arch/arm/boot/dts/lan966x-pcb8290.dts
> new file mode 100644
> index 000000000000..2e091180a64c
> --- /dev/null
> +++ b/arch/arm/boot/dts/lan966x-pcb8290.dts
> @@ -0,0 +1,175 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * lan966x-pcb8290.dts - Device Tree file for LAN966X-PCB8290 board
> + *
> + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Horatiu Vultur <horatiu.vultur@microchip.com>
> + */
> +/dts-v1/;
> +#include "lan966x.dtsi"
> +#include "dt-bindings/phy/phy-lan966x-serdes.h"
> +
> +/ {
> +	model = "Microchip EVB LAN9668";
> +	compatible = "microchip,lan9668-pcb8290", "microchip,lan9668", "microchip,lan966";
> +
> +	gpio-restart {
> +		compatible = "gpio-restart";
> +		gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
> +		priority = <200>;
> +	};
> +};
> +
> +&gpio {
> +	miim_a_pins: mdio-pins {
> +		/* MDC, MDIO */
> +		pins =  "GPIO_28", "GPIO_29";
> +		function = "miim_a";
> +	};
> +
> +	pps_out_pins: pps-out-pins {
> +		/* 1pps output */
> +		pins = "GPIO_38";
> +		function = "ptpsync_3";
> +	};
> +
> +	ptp_ext_pins: ptp-ext-pins {
> +		/* 1pps input */
> +		pins = "GPIO_35";
> +		function = "ptpsync_0";
> +	};
> +
> +	udc_pins: ucd-pins {
> +		/* VBUS_DET B */
> +		pins = "GPIO_8";
> +		function = "usb_slave_b";
> +	};
> +};
> +
> +&mdio0 {
> +	pinctrl-0 = <&miim_a_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +
> +	ext_phy0: ethernet-phy@7 {
> +		reg = <7>;
> +		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
> +	};
> +
> +	ext_phy1: ethernet-phy@8 {
> +		reg = <8>;
> +		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
> +	};
> +
> +	ext_phy2: ethernet-phy@9 {
> +		reg = <9>;
> +		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
> +	};
> +
> +	ext_phy3: ethernet-phy@10 {
> +		reg = <10>;
> +		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
> +	};
> +
> +	ext_phy4: ethernet-phy@15 {
> +		reg = <15>;
> +		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
> +	};
> +
> +	ext_phy5: ethernet-phy@16 {
> +		reg = <16>;
> +		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
> +	};
> +
> +	ext_phy6: ethernet-phy@17 {
> +		reg = <17>;
> +		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
> +	};
> +
> +	ext_phy7: ethernet-phy@18 {
> +		reg = <18>;
> +		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
> +	};
> +};
> +
> +&port0 {
> +	reg = <2>;
> +	phy-handle = <&ext_phy2>;
> +	phy-mode = "qsgmii";
> +	phys = <&serdes 0 SERDES6G(1)>;
> +	status = "okay";
> +};
> +
> +&port1 {
> +	reg = <3>;
> +	phy-handle = <&ext_phy3>;
> +	phy-mode = "qsgmii";
> +	phys = <&serdes 1 SERDES6G(1)>;
> +	status = "okay";
> +};
> +
> +&port2 {
> +	reg = <0>;
> +	phy-handle = <&ext_phy0>;
> +	phy-mode = "qsgmii";
> +	phys = <&serdes 2 SERDES6G(1)>;
> +	status = "okay";
> +};
> +
> +&port3 {
> +	reg = <1>;
> +	phy-handle = <&ext_phy1>;
> +	phy-mode = "qsgmii";
> +	phys = <&serdes 3 SERDES6G(1)>;
> +	status = "okay";
> +};
> +
> +&port4 {
> +	reg = <6>;
> +	phy-handle = <&ext_phy6>;
> +	phy-mode = "qsgmii";
> +	phys = <&serdes 4 SERDES6G(2)>;
> +	status = "okay";
> +};
> +
> +&port5 {
> +	reg = <7>;
> +	phy-handle = <&ext_phy7>;
> +	phy-mode = "qsgmii";
> +	phys = <&serdes 5 SERDES6G(2)>;
> +	status = "okay";
> +};
> +
> +&port6 {
> +	reg = <4>;
> +	phy-handle = <&ext_phy4>;
> +	phy-mode = "qsgmii";
> +	phys = <&serdes 6 SERDES6G(2)>;
> +	status = "okay";
> +};
> +
> +&port7 {
> +	reg = <5>;
> +	phy-handle = <&ext_phy5>;
> +	phy-mode = "qsgmii";
> +	phys = <&serdes 7 SERDES6G(2)>;
> +	status = "okay";
> +};
> +
> +&serdes {
> +	status = "okay";
> +};
> +
> +&switch {
> +	pinctrl-0 = <&pps_out_pins>, <&ptp_ext_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&udc {
> +	pinctrl-0 = <&udc_pins>;
> +	pinctrl-names = "default";
> +	atmel,vbus-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 05d8aef6e5d2..595e870750cd 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -788,6 +788,7 @@  dtb-$(CONFIG_SOC_IMXRT) += \
 dtb-$(CONFIG_SOC_LAN966) += \
 	lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \
 	lan966x-kontron-kswitch-d10-mmt-8g.dtb \
+	lan966x-pcb8290.dtb \
 	lan966x-pcb8291.dtb \
 	lan966x-pcb8309.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
diff --git a/arch/arm/boot/dts/lan966x-pcb8290.dts b/arch/arm/boot/dts/lan966x-pcb8290.dts
new file mode 100644
index 000000000000..2e091180a64c
--- /dev/null
+++ b/arch/arm/boot/dts/lan966x-pcb8290.dts
@@ -0,0 +1,175 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * lan966x-pcb8290.dts - Device Tree file for LAN966X-PCB8290 board
+ *
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Horatiu Vultur <horatiu.vultur@microchip.com>
+ */
+/dts-v1/;
+#include "lan966x.dtsi"
+#include "dt-bindings/phy/phy-lan966x-serdes.h"
+
+/ {
+	model = "Microchip EVB LAN9668";
+	compatible = "microchip,lan9668-pcb8290", "microchip,lan9668", "microchip,lan966";
+
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
+		priority = <200>;
+	};
+};
+
+&gpio {
+	miim_a_pins: mdio-pins {
+		/* MDC, MDIO */
+		pins =  "GPIO_28", "GPIO_29";
+		function = "miim_a";
+	};
+
+	pps_out_pins: pps-out-pins {
+		/* 1pps output */
+		pins = "GPIO_38";
+		function = "ptpsync_3";
+	};
+
+	ptp_ext_pins: ptp-ext-pins {
+		/* 1pps input */
+		pins = "GPIO_35";
+		function = "ptpsync_0";
+	};
+
+	udc_pins: ucd-pins {
+		/* VBUS_DET B */
+		pins = "GPIO_8";
+		function = "usb_slave_b";
+	};
+};
+
+&mdio0 {
+	pinctrl-0 = <&miim_a_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	ext_phy0: ethernet-phy@7 {
+		reg = <7>;
+		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
+	};
+
+	ext_phy1: ethernet-phy@8 {
+		reg = <8>;
+		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
+	};
+
+	ext_phy2: ethernet-phy@9 {
+		reg = <9>;
+		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
+	};
+
+	ext_phy3: ethernet-phy@10 {
+		reg = <10>;
+		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
+	};
+
+	ext_phy4: ethernet-phy@15 {
+		reg = <15>;
+		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
+	};
+
+	ext_phy5: ethernet-phy@16 {
+		reg = <16>;
+		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
+	};
+
+	ext_phy6: ethernet-phy@17 {
+		reg = <17>;
+		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
+	};
+
+	ext_phy7: ethernet-phy@18 {
+		reg = <18>;
+		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
+	};
+};
+
+&port0 {
+	reg = <2>;
+	phy-handle = <&ext_phy2>;
+	phy-mode = "qsgmii";
+	phys = <&serdes 0 SERDES6G(1)>;
+	status = "okay";
+};
+
+&port1 {
+	reg = <3>;
+	phy-handle = <&ext_phy3>;
+	phy-mode = "qsgmii";
+	phys = <&serdes 1 SERDES6G(1)>;
+	status = "okay";
+};
+
+&port2 {
+	reg = <0>;
+	phy-handle = <&ext_phy0>;
+	phy-mode = "qsgmii";
+	phys = <&serdes 2 SERDES6G(1)>;
+	status = "okay";
+};
+
+&port3 {
+	reg = <1>;
+	phy-handle = <&ext_phy1>;
+	phy-mode = "qsgmii";
+	phys = <&serdes 3 SERDES6G(1)>;
+	status = "okay";
+};
+
+&port4 {
+	reg = <6>;
+	phy-handle = <&ext_phy6>;
+	phy-mode = "qsgmii";
+	phys = <&serdes 4 SERDES6G(2)>;
+	status = "okay";
+};
+
+&port5 {
+	reg = <7>;
+	phy-handle = <&ext_phy7>;
+	phy-mode = "qsgmii";
+	phys = <&serdes 5 SERDES6G(2)>;
+	status = "okay";
+};
+
+&port6 {
+	reg = <4>;
+	phy-handle = <&ext_phy4>;
+	phy-mode = "qsgmii";
+	phys = <&serdes 6 SERDES6G(2)>;
+	status = "okay";
+};
+
+&port7 {
+	reg = <5>;
+	phy-handle = <&ext_phy5>;
+	phy-mode = "qsgmii";
+	phys = <&serdes 7 SERDES6G(2)>;
+	status = "okay";
+};
+
+&serdes {
+	status = "okay";
+};
+
+&switch {
+	pinctrl-0 = <&pps_out_pins>, <&ptp_ext_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&udc {
+	pinctrl-0 = <&udc_pins>;
+	pinctrl-names = "default";
+	atmel,vbus-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};