diff mbox series

[v6,06/10] clk: imx: Update pllv3 to support i.MXRT1170

Message ID 20220901183343.3188903-7-Mr.Bossman075@gmail.com (mailing list archive)
State Not Applicable
Headers show
Series Add support for i.MXRT1170-evk | expand

Commit Message

Jesse T Sept. 1, 2022, 6:33 p.m. UTC 
The i.MXRT1170 has a pll that has the multiplier bits inverted and
cannot be changed add IMX_PLLV3_GENERICV2.

The i.MXRT1170 also has the lock bit moved as well as the
power bit inverted the power bit also is in different locations on each
pll control register.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
V1 -> V2:
 - Nothing done
V2 -> V3:
 - Nothing done
V3 -> V4:
 - Nothing done
V4 -> V5:
 - Add __imx_clk_hw_pllv3 to change power bit
 - Add BM_PLL_POWER and imx_clk_hw_pllv3 to header
 - Remove imx_clk_hw_pll3_powerbit
V5 -> V6:
 - Fix __imx_clk_hw_pllv3 deffintion
 - Fix imx_clk_hw_pllv3 macro
 - Remove imx_clk_hw_pll3_powerbit
---
 drivers/clk/imx/clk-pllv3.c | 57 +++++++++++++++++++++++++++++++++----
 drivers/clk/imx/clk.h       | 11 +++++--
 2 files changed, 60 insertions(+), 8 deletions(-)

Comments

kernel test robot Sept. 2, 2022, 4:58 a.m. UTC | #1 
Hi Jesse,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on robh/for-next]
[also build test WARNING on soc/for-next linus/master v6.0-rc3 next-20220901]
[cannot apply to tip/timers/core]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Jesse-Taube/Add-support-for-i-MXRT1170-evk/20220902-023651
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm-defconfig
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/4949a69928402161dfceafc7c6efc708433f5fec
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Jesse-Taube/Add-support-for-i-MXRT1170-evk/20220902-023651
        git checkout 4949a69928402161dfceafc7c6efc708433f5fec
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/clk/imx/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   In file included from include/linux/bits.h:6,
                    from drivers/clk/imx/clk-imx6q.c:9:
   drivers/clk/imx/clk-imx6q.c: In function 'imx6q_clocks_init':
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6q.c:477:33: note: in expansion of macro 'imx_clk_hw_pllv3'
     477 |         hws[IMX6QDL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS,     "pll1", "osc", base + 0x00, 0x7f);
         |                                 ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6q.c:478:33: note: in expansion of macro 'imx_clk_hw_pllv3'
     478 |         hws[IMX6QDL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
         |                                 ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6q.c:479:33: note: in expansion of macro 'imx_clk_hw_pllv3'
     479 |         hws[IMX6QDL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB,     "pll3", "osc", base + 0x10, 0x3);
         |                                 ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6q.c:480:33: note: in expansion of macro 'imx_clk_hw_pllv3'
     480 |         hws[IMX6QDL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV,      "pll4", "osc", base + 0x70, 0x7f);
         |                                 ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6q.c:481:33: note: in expansion of macro 'imx_clk_hw_pllv3'
     481 |         hws[IMX6QDL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV,      "pll5", "osc", base + 0xa0, 0x7f);
         |                                 ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6q.c:482:33: note: in expansion of macro 'imx_clk_hw_pllv3'
     482 |         hws[IMX6QDL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET,    "pll6", "osc", base + 0xe0, 0x3);
         |                                 ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6q.c:483:33: note: in expansion of macro 'imx_clk_hw_pllv3'
     483 |         hws[IMX6QDL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB,     "pll7", "osc", base + 0x20, 0x3);
         |                                 ^~~~~~~~~~~~~~~~
--
   In file included from include/linux/bits.h:6,
                    from drivers/clk/imx/clk-imx6sl.c:6:
   drivers/clk/imx/clk-imx6sl.c: In function 'imx6sl_clocks_init':
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sl.c:217:32: note: in expansion of macro 'imx_clk_hw_pllv3'
     217 |         hws[IMX6SL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS,     "pll1", "osc", base + 0x00, 0x7f);
         |                                ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sl.c:218:32: note: in expansion of macro 'imx_clk_hw_pllv3'
     218 |         hws[IMX6SL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
         |                                ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sl.c:219:32: note: in expansion of macro 'imx_clk_hw_pllv3'
     219 |         hws[IMX6SL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB,     "pll3", "osc", base + 0x10, 0x3);
         |                                ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sl.c:220:32: note: in expansion of macro 'imx_clk_hw_pllv3'
     220 |         hws[IMX6SL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV,      "pll4", "osc", base + 0x70, 0x7f);
         |                                ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sl.c:221:32: note: in expansion of macro 'imx_clk_hw_pllv3'
     221 |         hws[IMX6SL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV,      "pll5", "osc", base + 0xa0, 0x7f);
         |                                ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sl.c:222:32: note: in expansion of macro 'imx_clk_hw_pllv3'
     222 |         hws[IMX6SL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET,    "pll6", "osc", base + 0xe0, 0x3);
         |                                ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sl.c:223:32: note: in expansion of macro 'imx_clk_hw_pllv3'
     223 |         hws[IMX6SL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB,     "pll7", "osc", base + 0x20, 0x3);
         |                                ^~~~~~~~~~~~~~~~
--
   In file included from include/linux/bits.h:6,
                    from include/linux/bitops.h:6,
                    from include/linux/kernel.h:22,
                    from include/linux/clk.h:13,
                    from drivers/clk/imx/clk-imx6sll.c:8:
   drivers/clk/imx/clk-imx6sll.c: In function 'imx6sll_clocks_init':
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sll.c:123:33: note: in expansion of macro 'imx_clk_hw_pllv3'
     123 |         hws[IMX6SLL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS,  "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
         |                                 ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sll.c:124:33: note: in expansion of macro 'imx_clk_hw_pllv3'
     124 |         hws[IMX6SLL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
         |                                 ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sll.c:125:33: note: in expansion of macro 'imx_clk_hw_pllv3'
     125 |         hws[IMX6SLL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB,  "pll3", "pll3_bypass_src", base + 0x10, 0x3);
         |                                 ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sll.c:126:33: note: in expansion of macro 'imx_clk_hw_pllv3'
     126 |         hws[IMX6SLL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV,   "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
         |                                 ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sll.c:127:33: note: in expansion of macro 'imx_clk_hw_pllv3'
     127 |         hws[IMX6SLL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV,   "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
         |                                 ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sll.c:128:33: note: in expansion of macro 'imx_clk_hw_pllv3'
     128 |         hws[IMX6SLL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET,         "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
         |                                 ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sll.c:129:33: note: in expansion of macro 'imx_clk_hw_pllv3'
     129 |         hws[IMX6SLL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB,  "pll7", "pll7_bypass_src", base + 0x20, 0x3);
         |                                 ^~~~~~~~~~~~~~~~
--
   In file included from include/linux/bits.h:6,
                    from drivers/clk/imx/clk-imx6sx.c:7:
   drivers/clk/imx/clk-imx6sx.c: In function 'imx6sx_clocks_init':
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sx.c:160:32: note: in expansion of macro 'imx_clk_hw_pllv3'
     160 |         hws[IMX6SX_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS,     "pll1", "osc", base + 0x00, 0x7f);
         |                                ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sx.c:161:32: note: in expansion of macro 'imx_clk_hw_pllv3'
     161 |         hws[IMX6SX_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
         |                                ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sx.c:162:32: note: in expansion of macro 'imx_clk_hw_pllv3'
     162 |         hws[IMX6SX_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB,     "pll3", "osc", base + 0x10, 0x3);
         |                                ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sx.c:163:32: note: in expansion of macro 'imx_clk_hw_pllv3'
     163 |         hws[IMX6SX_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV,      "pll4", "osc", base + 0x70, 0x7f);
         |                                ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sx.c:164:32: note: in expansion of macro 'imx_clk_hw_pllv3'
     164 |         hws[IMX6SX_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV,      "pll5", "osc", base + 0xa0, 0x7f);
         |                                ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sx.c:165:32: note: in expansion of macro 'imx_clk_hw_pllv3'
     165 |         hws[IMX6SX_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET,    "pll6", "osc", base + 0xe0, 0x3);
         |                                ^~~~~~~~~~~~~~~~
>> include/vdso/bits.h:7:33: warning: conversion from 'long unsigned int' to 'u8' {aka 'unsigned char'} changes value from '4096' to '0' [-Woverflow]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ^~~~~~~~~~~~~~~
   drivers/clk/imx/clk.h:9:33: note: in expansion of macro 'BIT'
       9 | #define BM_PLL_POWER            BIT(12)
         |                                 ^~~
   drivers/clk/imx/clk.h:108:69: note: in expansion of macro 'BM_PLL_POWER'
     108 |         __imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
         |                                                                     ^~~~~~~~~~~~
   drivers/clk/imx/clk-imx6sx.c:166:32: note: in expansion of macro 'imx_clk_hw_pllv3'
     166 |         hws[IMX6SX_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB,     "pll7", "osc", base + 0x20, 0x3);
         |                                ^~~~~~~~~~~~~~~~
..


vim +7 include/vdso/bits.h

3945ff37d2f48d Vincenzo Frascino 2020-03-20  6  
3945ff37d2f48d Vincenzo Frascino 2020-03-20 @7  #define BIT(nr)			(UL(1) << (nr))
3945ff37d2f48d Vincenzo Frascino 2020-03-20  8
diff mbox series

Patch

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index eea32f87c60a..68b1498cafe1 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -21,8 +21,8 @@ 
 #define PLL_VF610_NUM_OFFSET	0x20
 #define PLL_VF610_DENOM_OFFSET	0x30
 
-#define BM_PLL_POWER		(0x1 << 12)
 #define BM_PLL_LOCK		(0x1 << 31)
+#define BM_PLL_LOCK_V2		(0x1 << 29)
 #define IMX7_ENET_PLL_POWER	(0x1 << 5)
 #define IMX7_DDR_PLL_POWER	(0x1 << 20)
 
@@ -34,6 +34,7 @@ 
  * @base:	 base address of PLL registers
  * @power_bit:	 pll power bit mask
  * @powerup_set: set power_bit to power up the PLL
+ * @lock_bit:	 pll lock bit mask
  * @div_mask:	 mask of divider bits
  * @div_shift:	 shift of divider bits
  * @ref_clock:	reference clock rate
@@ -48,6 +49,7 @@  struct clk_pllv3 {
 	void __iomem	*base;
 	u32		power_bit;
 	bool		powerup_set;
+	u32		lock_bit;
 	u32		div_mask;
 	u32		div_shift;
 	unsigned long	ref_clock;
@@ -65,7 +67,7 @@  static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
 	if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
 		return 0;
 
-	return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK,
+	return readl_relaxed_poll_timeout(pll->base, val, val & pll->lock_bit,
 					  500, PLL_LOCK_TIMEOUT);
 }
 
@@ -101,7 +103,7 @@  static int clk_pllv3_is_prepared(struct clk_hw *hw)
 {
 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
 
-	if (readl_relaxed(pll->base) & BM_PLL_LOCK)
+	if (readl_relaxed(pll->base) & pll->lock_bit)
 		return 1;
 
 	return 0;
@@ -155,6 +157,39 @@  static const struct clk_ops clk_pllv3_ops = {
 	.set_rate	= clk_pllv3_set_rate,
 };
 
+static int clk_pllv3_genericv2_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)
+{
+	struct clk_pllv3 *pll = to_clk_pllv3(hw);
+	u32 val, div;
+
+	div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
+	val = (div == 0) ? parent_rate * 22 : parent_rate * 20;
+
+	if (rate == val)
+		return 0;
+
+	return -EINVAL;
+}
+
+static unsigned long clk_pllv3_genericv2_recalc_rate(struct clk_hw *hw,
+					   unsigned long parent_rate)
+{
+	struct clk_pllv3 *pll = to_clk_pllv3(hw);
+	u32 div = (readl_relaxed(pll->base) >> pll->div_shift)  & pll->div_mask;
+
+	return (div == 0) ? parent_rate * 22 : parent_rate * 20;
+}
+
+static const struct clk_ops clk_pllv3_genericv2_ops = {
+	.prepare	= clk_pllv3_prepare,
+	.unprepare	= clk_pllv3_unprepare,
+	.is_prepared	= clk_pllv3_is_prepared,
+	.recalc_rate	= clk_pllv3_genericv2_recalc_rate,
+	.round_rate	= clk_pllv3_round_rate,
+	.set_rate	= clk_pllv3_genericv2_set_rate,
+};
+
 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
 					       unsigned long parent_rate)
 {
@@ -407,9 +442,9 @@  static const struct clk_ops clk_pllv3_enet_ops = {
 	.recalc_rate	= clk_pllv3_enet_recalc_rate,
 };
 
-struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
+struct clk_hw *__imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
 			  const char *parent_name, void __iomem *base,
-			  u32 div_mask)
+			  u32 div_mask, u8 pwr_bit)
 {
 	struct clk_pllv3 *pll;
 	const struct clk_ops *ops;
@@ -421,11 +456,21 @@  struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
 	if (!pll)
 		return ERR_PTR(-ENOMEM);
 
-	pll->power_bit = BM_PLL_POWER;
+	pll->power_bit = pwr_bit;
+	pll->lock_bit = BM_PLL_LOCK;
 	pll->num_offset = PLL_NUM_OFFSET;
 	pll->denom_offset = PLL_DENOM_OFFSET;
 
 	switch (type) {
+	case IMX_PLLV3_GENERICV2:
+		pll->lock_bit = BM_PLL_LOCK_V2;
+		pll->powerup_set = true;
+		ops = &clk_pllv3_genericv2_ops;
+		break;
+	case IMX_PLLV3_SYSV2:
+		pll->lock_bit = BM_PLL_LOCK_V2;
+		pll->powerup_set = true;
+		fallthrough;
 	case IMX_PLLV3_SYS:
 		ops = &clk_pllv3_sys_ops;
 		break;
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 5061a06468df..124f4a79537f 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -6,6 +6,8 @@ 
 #include <linux/spinlock.h>
 #include <linux/clk-provider.h>
 
+#define BM_PLL_POWER		BIT(12)
+
 extern spinlock_t imx_ccm_lock;
 extern bool mcore_booted;
 
@@ -102,6 +104,9 @@  extern struct imx_fracn_gppll_clk imx_fracn_gppll;
 	to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
 				cgr_val, cgr_mask, clk_gate_flags, lock, share_count))
 
+#define imx_clk_hw_pllv3(type, name, parent_name, base, div_mask) \
+	__imx_clk_hw_pllv3(type, name, parent_name, base, div_mask, BM_PLL_POWER)
+
 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
 	to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
 
@@ -242,6 +247,8 @@  struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
 
 enum imx_pllv3_type {
 	IMX_PLLV3_GENERIC,
+	IMX_PLLV3_GENERICV2,
+	IMX_PLLV3_SYSV2,
 	IMX_PLLV3_SYS,
 	IMX_PLLV3_USB,
 	IMX_PLLV3_USB_VF610,
@@ -253,8 +260,8 @@  enum imx_pllv3_type {
 	IMX_PLLV3_AV_IMX7,
 };
 
-struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
-		const char *parent_name, void __iomem *base, u32 div_mask);
+struct clk_hw *__imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
+		const char *parent_name, void __iomem *base, u32 div_mask, u8 pwr_bit);
 
 #define PLL_1416X_RATE(_rate, _m, _p, _s)		\
 	{						\