| Message ID | 20230612-fasting-floss-0bc05a08bc7a@spud (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | c9a5aa0e53d073d99559aedba9725c4220aafe11 |
| Headers | show |
| Series | [GIT,PULL] RISC-V Devicetrees for v6.5 | expand |
Hello: This pull request was applied to soc/soc.git (arm/fixes) by Arnd Bergmann <arnd@arndb.de>: On Mon, 12 Jun 2023 19:23:14 +0100 you wrote: > Hey Arnd, > > A wee bunch of changes this time around as a bunch of the jh7110 stuff > is still blocked on clock drivers. This'll probably be my only PR for > the window, haven't got anything SoC-driver wise & it's unlikely that > any of the other bits will be ready in the coming week. > > [...] Here is the summary with links: - [GIT,PULL] RISC-V Devicetrees for v6.5 https://git.kernel.org/soc/soc/c/c9a5aa0e53d0 You are awesome, thank you!
Hey Arnd, A wee bunch of changes this time around as a bunch of the jh7110 stuff is still blocked on clock drivers. This'll probably be my only PR for the window, haven't got anything SoC-driver wise & it's unlikely that any of the other bits will be ready in the coming week. Thanks, Conor. The following changes since commit ac9a78681b921877518763ba0e89202254349d1b: Linux 6.4-rc1 (2023-05-07 13:34:35 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-dt-for-v6.5 for you to fetch changes up to e2c510d6d630fe6593a0cf87531913b4b08ebeb1: riscv: dts: starfive: Add cpu scaling for JH7110 SoC (2023-06-06 12:32:06 +0100) ---------------------------------------------------------------- RISC-V Devicetrees for v6.5 StarFive: Watchdog nodes for both the JH7110 & its forerunner, the JH7100. PMU, P being power, support for the JH7110. PMIC and frequency scaling support for the JH7110 equipped VisionFive 2. Most of the DT bits for the JH7110, and the SBCs using it, are pending support for one of the clock controllers, so it's a smaller set of changes than I would have hoped for. Misc: Pick up some dt-binding cleanup that Palmer assigned to me & had no uptake from the respective maintainers. My powers of estimation failed me again, with part of my motivation for picking them up being the addition of new platforms that ended up not making it. Hopefully next window for those, as they were relatively close. Exclude the Allwinner and Renesas subdirectories from the Misc. MAINTAINERS entry, since I do not take care of those. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> ---------------------------------------------------------------- Conor Dooley (1): MAINTAINERS: exclude maintained subdirs in RISC-V misc DT entry Geert Uytterhoeven (2): dt-bindings: timer: sifive,clint: Clean up compatible value section dt-bindings: interrupt-controller: sifive,plic: Sort compatible values Mason Huo (2): riscv: dts: starfive: Enable axp15060 pmic for cpufreq riscv: dts: starfive: Add cpu scaling for JH7110 SoC Walker Chen (1): riscv: dts: starfive: Add PMU controller node Xingyu Wu (2): riscv: dts: starfive: jh7100: Add watchdog node riscv: dts: starfive: jh7110: Add watchdog node .../interrupt-controller/sifive,plic-1.0.0.yaml | 2 +- .../devicetree/bindings/timer/sifive,clint.yaml | 21 ++++----- MAINTAINERS | 2 + arch/riscv/boot/dts/starfive/jh7100.dtsi | 10 +++++ .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 33 ++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 50 ++++++++++++++++++++++ 6 files changed, 104 insertions(+), 14 deletions(-)