| Message ID | 20231015-outmatch-tragedy-228f91d396b5@spud (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | e4078ebbddf69f5a82f164dc07d50321b7f641cf |
| Headers | show |
| Series | [GIT,PULL] RISC-V Devicetrees for v6.6-final | expand |
Hello: This pull request was applied to soc/soc.git (arm/fixes) by Arnd Bergmann <arnd@arndb.de>: On Sun, 15 Oct 2023 13:26:47 +0100 you wrote: > Hey Arnd, > > Just a single patch for you here, been quiet on the fixes front :) > > Thanks, > Conor. > > [...] Here is the summary with links: - [GIT,PULL] RISC-V Devicetrees for v6.6-final https://git.kernel.org/soc/soc/c/e4078ebbddf6 You are awesome, thank you!
Hey Arnd, Just a single patch for you here, been quiet on the fixes front :) Thanks, Conor. The following changes since commit 1558209533f140624a00408bdab796ab3f309450: riscv: dts: starfive: visionfive 2: Fix uart0 pins sort order (2023-09-13 14:24:56 +0100) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-dt-for-v6.6-final for you to fetch changes up to cf98fe6b579e55aa71b6197e34c112b51f0c2a66: riscv: dts: starfive: visionfive 2: correct spi's ss pin (2023-10-12 10:23:23 +0100) ---------------------------------------------------------------- RISC-V Devicetrees for v6.6-final A single fix for the Starfive VisionFive 2 platform so that chip select for SPI matches the vendor documentation. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> ---------------------------------------------------------------- Nam Cao (1): riscv: dts: starfive: visionfive 2: correct spi's ss pin arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)