| Message ID | 20231221-catatonic-monday-d4c61283b136@spud (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 41ab5e162569a17070a03d4964750b884cb90595 |
| Headers | show |
| Series | [GIT,PULL] RISC-V cache drivers for v6.8 | expand |
Hello: This pull request was applied to soc/soc.git (for-next) by Arnd Bergmann <arnd@arndb.de>: On Thu, 21 Dec 2023 12:57:53 +0000 you wrote: > Hey Arnd, > > Please pull the move of the ccache driver out of drivers/soc and the > addition of support for the non-standard non-coherent cache operations > on the jh7100. Despite it being an early(ish) SoC and being succeeded by > the jh7110, there's still people actively adding mainline support for > some of the peripherals etc. > > [...] Here is the summary with links: - [GIT,PULL] RISC-V cache drivers for v6.8 https://git.kernel.org/soc/soc/c/41ab5e162569 You are awesome, thank you!
Hey Arnd, Please pull the move of the ccache driver out of drivers/soc and the addition of support for the non-standard non-coherent cache operations on the jh7100. Despite it being an early(ish) SoC and being succeeded by the jh7110, there's still people actively adding mainline support for some of the peripherals etc. Cheers, Conor. The following changes since commit b85ea95d086471afb4ad062012a4d73cd328fa86: Linux 6.7-rc1 (2023-11-12 16:19:07 -0800) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-cache-for-v6.8 for you to fetch changes up to 9a9e8d8d2b6e61a516cbb8a43c5cec51c065ffa4: riscv: errata: Make ERRATA_STARFIVE_JH7100 depend on !DMA_DIRECT_REMAP (2023-12-16 23:37:38 +0000) ---------------------------------------------------------------- RISC-V cache drivers for v6.8 The SiFive composable cache driver moves to the cache driver subdirectory from the drivers/soc and grows support for non-coherent cache operations. The immediate user for these is the jh7100 SoC, that a rake of people have on VisionFive v1 or Beagle-V Starlight boards. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> ---------------------------------------------------------------- Conor Dooley (1): soc: sifive: shunt ccache driver to drivers/cache Emil Renner Berthing (4): dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible soc: sifive: ccache: Add StarFive JH7100 support riscv: errata: Add StarFive JH7100 errata riscv: errata: Make ERRATA_STARFIVE_JH7100 depend on !DMA_DIRECT_REMAP .../devicetree/bindings/cache/sifive,ccache0.yaml | 6 ++- MAINTAINERS | 14 ++--- arch/riscv/Kconfig.errata | 19 +++++++ drivers/cache/Kconfig | 6 +++ drivers/cache/Makefile | 3 +- drivers/{soc/sifive => cache}/sifive_ccache.c | 62 +++++++++++++++++++++- drivers/soc/Kconfig | 1 - drivers/soc/Makefile | 1 - drivers/soc/sifive/Kconfig | 10 ---- drivers/soc/sifive/Makefile | 3 -- 10 files changed, 99 insertions(+), 26 deletions(-) rename drivers/{soc/sifive => cache}/sifive_ccache.c (81