| Message ID | 20240909-hybrid-groovy-601a33b5b309@spud (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 0e7af99aef5f58b4bae00e45fd1c2626a987f7bb |
| Headers | show |
| Series | [GIT,PULL] RISC-V soc fixes for v6.11-final | expand |
Hello: This pull request was applied to soc/soc.git (arm/fixes) by Arnd Bergmann <arnd@arndb.de>: On Mon, 9 Sep 2024 15:33:36 +0100 you wrote: > Hey Arnd, > > Here's the fix that was being discussed on IRC over the weekend. > > Cheers, > conor. > > [...] Here is the summary with links: - [GIT,PULL] RISC-V soc fixes for v6.11-final https://git.kernel.org/soc/soc/c/0e7af99aef5f You are awesome, thank you!
Hey Arnd, Here's the fix that was being discussed on IRC over the weekend. Cheers, conor. The following changes since commit 591940e22e287fb64ac07be275e343d860cb72d6: firmware: microchip: fix incorrect error report of programming:timeout on success (2024-08-22 20:47:16 +0100) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-soc-fixes-for-v6.11-final for you to fetch changes up to 61f2e8a3a94175dbbaad6a54f381b2a505324610: riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz (2024-09-08 23:20:19 +0100) ---------------------------------------------------------------- RISC-V soc fixes for v6.11-final StarFive: A fix to return one of the clocks on the JH7110 from 1 GHz to 1.5 GHz Signed-off-by: Conor Dooley <conor.dooley@microchip.com> ---------------------------------------------------------------- Xingyu Wu (1): riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)