| Message ID | 20240910-annex-ravage-07d63041a7c5@spud (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 3c557d0062bc73e430d496710819bc63ded439ca |
| Headers | show |
| Series | [GIT,PULL] RISC-V config for v6.12 | expand |
Hello: This pull request was applied to soc/soc.git (for-next) by Arnd Bergmann <arnd@arndb.de>: On Tue, 10 Sep 2024 23:02:17 +0100 you wrote: > Hey Arnd, > > Practically nothing for you this cycle, so this will be my only PR. > There's both Microchip and Spacemit stuff on the lists, but none of it > ready for this cycle. > > Cheers, > Conor. > > [...] Here is the summary with links: - [GIT,PULL] RISC-V config for v6.12 https://git.kernel.org/soc/soc/c/3c557d0062bc You are awesome, thank you!
Hey Arnd, Practically nothing for you this cycle, so this will be my only PR. There's both Microchip and Spacemit stuff on the lists, but none of it ready for this cycle. Cheers, Conor. The following changes since commit 8400291e289ee6b2bf9779ff1c83a291501f017b: Linux 6.11-rc1 (2024-07-28 14:19:55 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-config-for-v6.12 for you to fetch changes up to 72160ec6cb12613663f26d89049b95f8dc9fa000: riscv: defconfig: Enable pinctrl support for CV18XX Series SoC (2024-09-09 12:55:53 +0100) ---------------------------------------------------------------- RISC-V config for v6.12 Two patches, enabling clock and pinctrl support in defconfig for Sopghgo devices. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> ---------------------------------------------------------------- Chen Wang (1): riscv: defconfig: sophgo: enable clks for sg2042 Inochi Amaoto (1): riscv: defconfig: Enable pinctrl support for CV18XX Series SoC arch/riscv/configs/defconfig | 7 +++++++ 1 file changed, 7 insertions(+)