[GIT,PULL] RISC-V soc fixes for v6.12-rc6

Message ID	20241031-colossal-cassette-617817c9bec3@spud (mailing list archive)
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Headers	show Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E40D514831D for <soc@lists.linux.dev>; Thu, 31 Oct 2024 12:22:21 +0000 (UTC) Date: Thu, 31 Oct 2024 12:22:18 +0000 From: Conor Dooley <conor@kernel.org> To: soc@kernel.org Cc: conor@kernel.org, linux-riscv@lists.infradead.org Subject: [GIT PULL] RISC-V soc fixes for v6.12-rc6 Message-ID: <20241031-colossal-cassette-617817c9bec3@spud> Precedence: bulk MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="kTm0+sFzuK+Ucblh" Content-Disposition: inline
Series	[GIT,PULL] RISC-V soc fixes for v6.12-rc6 \| expand [GIT,PULL] RISC-V soc fixes for v6.12-rc6

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20241031-colossal-cassette-617817c9bec3@spud (mailing list archive)

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Date: Thu, 31 Oct 2024 12:22:18 +0000
From: Conor Dooley <conor@kernel.org>
To: soc@kernel.org
Cc: conor@kernel.org, linux-riscv@lists.infradead.org
Subject: [GIT PULL] RISC-V soc fixes for v6.12-rc6
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[GIT,PULL] RISC-V soc fixes for v6.12-rc6 | expand

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Conor Dooley Oct. 31, 2024, 12:22 p.m. UTC

Hey Arnd,

Please pull some fixes that I have accumulated for this cycle.

Cheers,
Conor.

The following changes since commit 8e929cb546ee42c9a61d24fae60605e9e3192354:

  Linux 6.12-rc3 (2024-10-13 14:33:32 -0700)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-soc-fixes-for-v6.12-rc6

for you to fetch changes up to 384f2024e1a100b9b977a697f5e7cb151b00550d:

  MAINTAINERS: invert Misc RISC-V SoC Support's pattern (2024-10-24 16:27:10 +0100)

----------------------------------------------------------------
RISC-V soc fixes for v6.12-rc6

StarFive:
Two minor dts fixes, one setting the correct eth phy delay parameters
and one disabling unused nodes that caused warnings at probe time.

Firmware:
Fix the poll_complete() implementation in the auto-update driver so that
it behaves as the framework expects.

Misc:
Update the maintainer pattern for my dts entry, so that it covers
the specific platforms listed , rather than including all riscv
platforms with the list platforms excluded.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

----------------------------------------------------------------
Conor Dooley (3):
      firmware: microchip: auto-update: fix poll_complete() to not report spurious timeout errors
      riscv: dts: starfive: disable unused csi/camss nodes
      MAINTAINERS: invert Misc RISC-V SoC Support's pattern

E Shattow (1):
      riscv: dts: starfive: Update ethernet phy0 delay parameter values for Star64

 MAINTAINERS                                        | 10 +++---
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi    |  2 --
 .../boot/dts/starfive/jh7110-pine64-star64.dts     |  3 +-
 drivers/firmware/microchip/mpfs-auto-update.c      | 42 ++++------------------
 4 files changed, 12 insertions(+), 45 deletions(-)

[GIT,PULL] RISC-V soc fixes for v6.12-rc6

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