| Message ID | 20250209220646.1090868-9-alexander.sverdlin@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64 support for Milk-V Duo Module 01 EVB | expand |
On Sun, Feb 09, 2025 at 11:06:33PM +0100, Alexander Sverdlin wrote: > Add reset controller node and required sysctl nodes. > > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> > --- > arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi > index 53834b0658b2..d793b6db4ed1 100644 > --- a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi > @@ -309,5 +309,21 @@ dmac: dma-controller@4330000 { > snps,data-width = <4>; > status = "disabled"; > }; > + > + rtcsys_ctrl: syscon@5025000 { > + compatible = "sophgo,cv1800-rtcsys-ctrl", "syscon"; > + reg = <0x05025000 0x1000>; > + }; > + > + rtcsys_core: syscon@5026000 { > + compatible = "sophgo,cv1800-rtcsys-core", "syscon"; > + reg = <0x05026000 0x1000>; > + }; > + > + soc-reset { > + compatible = "sophgo,cv1800-reset"; > + sophgo,rtcsys-ctrl = <&rtcsys_ctrl>; > + sophgo,rtcsys-core = <&rtcsys_core>; > + }; I think these node is not suitable for riscv. It should use SBI SRST extension to restart. Regards, Inochi
On 09/02/2025 23:06, Alexander Sverdlin wrote: > Add reset controller node and required sysctl nodes. > > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> > --- > arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi > index 53834b0658b2..d793b6db4ed1 100644 > --- a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi > @@ -309,5 +309,21 @@ dmac: dma-controller@4330000 { > snps,data-width = <4>; > status = "disabled"; > }; > + > + rtcsys_ctrl: syscon@5025000 { > + compatible = "sophgo,cv1800-rtcsys-ctrl", "syscon"; > + reg = <0x05025000 0x1000>; > + }; > + > + rtcsys_core: syscon@5026000 { > + compatible = "sophgo,cv1800-rtcsys-core", "syscon"; > + reg = <0x05026000 0x1000>; > + }; > + > + soc-reset { > + compatible = "sophgo,cv1800-reset"; Nope. You cannot have non-MMIO nodes in SoC which proves this is not a real SoC device. Neither compatible, nor its placement is correct. Depending on the hardware design, this most likely is just part of your 5025000 block. Best regards, Krzysztof
Thanks for quick feedback Inochi! On Mon, 2025-02-10 at 13:13 +0800, Inochi Amaoto wrote: > On Sun, Feb 09, 2025 at 11:06:33PM +0100, Alexander Sverdlin wrote: > > Add reset controller node and required sysctl nodes. > > > > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> > > --- > > arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi > > index 53834b0658b2..d793b6db4ed1 100644 > > --- a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi > > +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi > > @@ -309,5 +309,21 @@ dmac: dma-controller@4330000 { > > snps,data-width = <4>; > > status = "disabled"; > > }; > > + > > > + rtcsys_ctrl: syscon@5025000 { > > + compatible = "sophgo,cv1800-rtcsys-ctrl", "syscon"; > > + reg = <0x05025000 0x1000>; > > + }; > > + > > + rtcsys_core: syscon@5026000 { > > + compatible = "sophgo,cv1800-rtcsys-core", "syscon"; > > + reg = <0x05026000 0x1000>; > > + }; > > + > > + soc-reset { > > + compatible = "sophgo,cv1800-reset"; > > + sophgo,rtcsys-ctrl = <&rtcsys_ctrl>; > > + sophgo,rtcsys-core = <&rtcsys_core>; > > + }; > > I think these node is not suitable for riscv. It should use SBI SRST > extension to restart. Independent from the particular form, or its correctness, this is still HW description, right? It would be a "policy" for the kernel configuration, if the particular build would rely on the FW or a kernel driver to reboot. In other words, the HW block remains in place, no matter if it's controlled by a kernel module or a FW. What the point in hiding it from the RiscV part of DT, keeping on ARM64 side only?
On Mon, Feb 10, 2025 at 12:47:59PM +0100, Alexander Sverdlin wrote: > Thanks for quick feedback Inochi! > > On Mon, 2025-02-10 at 13:13 +0800, Inochi Amaoto wrote: > > On Sun, Feb 09, 2025 at 11:06:33PM +0100, Alexander Sverdlin wrote: > > > Add reset controller node and required sysctl nodes. > > > > > > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> > > > --- > > > arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 16 ++++++++++++++++ > > > 1 file changed, 16 insertions(+) > > > > > > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi > > > index 53834b0658b2..d793b6db4ed1 100644 > > > --- a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi > > > +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi > > > @@ -309,5 +309,21 @@ dmac: dma-controller@4330000 { > > > snps,data-width = <4>; > > > status = "disabled"; > > > }; > > > + > > > > > + rtcsys_ctrl: syscon@5025000 { > > > + compatible = "sophgo,cv1800-rtcsys-ctrl", "syscon"; > > > + reg = <0x05025000 0x1000>; > > > + }; > > > + > > > + rtcsys_core: syscon@5026000 { > > > + compatible = "sophgo,cv1800-rtcsys-core", "syscon"; > > > + reg = <0x05026000 0x1000>; > > > + }; > > > + > > > + soc-reset { > > > + compatible = "sophgo,cv1800-reset"; > > > + sophgo,rtcsys-ctrl = <&rtcsys_ctrl>; > > > + sophgo,rtcsys-core = <&rtcsys_core>; > > > + }; > > > > I think these node is not suitable for riscv. It should use SBI SRST > > extension to restart. > > Independent from the particular form, or its correctness, this is still HW > description, right? It would be a "policy" for the kernel configuration, if > the particular build would rely on the FW or a kernel driver to reboot. > > In other words, the HW block remains in place, no matter if it's controlled > by a kernel module or a FW. What the point in hiding it from the RiscV part > of DT, keeping on ARM64 side only? > Yeah, I have make a mistake, the device is needed. SBI need these device definition to handle some power event. Regards, Inochi
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi index 53834b0658b2..d793b6db4ed1 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi @@ -309,5 +309,21 @@ dmac: dma-controller@4330000 { snps,data-width = <4>; status = "disabled"; }; + + rtcsys_ctrl: syscon@5025000 { + compatible = "sophgo,cv1800-rtcsys-ctrl", "syscon"; + reg = <0x05025000 0x1000>; + }; + + rtcsys_core: syscon@5026000 { + compatible = "sophgo,cv1800-rtcsys-core", "syscon"; + reg = <0x05026000 0x1000>; + }; + + soc-reset { + compatible = "sophgo,cv1800-reset"; + sophgo,rtcsys-ctrl = <&rtcsys_ctrl>; + sophgo,rtcsys-core = <&rtcsys_core>; + }; }; };
Add reset controller node and required sysctl nodes. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> --- arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)