| Message ID | 20250415072724.3565533-8-peter.chen@cixtech.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: Introduce CIX P1 (SKY1) SoC | expand |
On 15/04/2025 09:27, Peter Chen wrote: > At CIX SoC platforms, the clock handling uses Arm SCMI protocol, > the physical clock access is at sub processor, so it needs to enable > mailbox by default. > > Signed-off-by: Peter Chen <peter.chen@cixtech.com> > --- > arch/arm64/configs/defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > index c8a8fdb0bedb..4e9805c5bcc3 100644 > --- a/arch/arm64/configs/defconfig > +++ b/arch/arm64/configs/defconfig > @@ -1424,6 +1424,7 @@ CONFIG_BCM2835_MBOX=y > CONFIG_QCOM_APCS_IPC=y > CONFIG_MTK_ADSP_MBOX=m > CONFIG_QCOM_IPCC=y > +CONFIG_CIX_MBOX=y Squash the patch. Don't create one patch per one config change. Best regards, Krzysztof
On 25-04-16 08:35:03, Krzysztof Kozlowski wrote: > EXTERNAL EMAIL > > On 15/04/2025 09:27, Peter Chen wrote: > > At CIX SoC platforms, the clock handling uses Arm SCMI protocol, > > the physical clock access is at sub processor, so it needs to enable > > mailbox by default. > > > > Signed-off-by: Peter Chen <peter.chen@cixtech.com> > > --- > > arch/arm64/configs/defconfig | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > > index c8a8fdb0bedb..4e9805c5bcc3 100644 > > --- a/arch/arm64/configs/defconfig > > +++ b/arch/arm64/configs/defconfig > > @@ -1424,6 +1424,7 @@ CONFIG_BCM2835_MBOX=y > > CONFIG_QCOM_APCS_IPC=y > > CONFIG_MTK_ADSP_MBOX=m > > CONFIG_QCOM_IPCC=y > > +CONFIG_CIX_MBOX=y > Squash the patch. Don't create one patch per one config change. > Even for two different configurations? One for SoC, and the another is for device driver.
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index c8a8fdb0bedb..4e9805c5bcc3 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1424,6 +1424,7 @@ CONFIG_BCM2835_MBOX=y CONFIG_QCOM_APCS_IPC=y CONFIG_MTK_ADSP_MBOX=m CONFIG_QCOM_IPCC=y +CONFIG_CIX_MBOX=y CONFIG_ROCKCHIP_IOMMU=y CONFIG_TEGRA_IOMMU_SMMU=y CONFIG_ARM_SMMU=y
At CIX SoC platforms, the clock handling uses Arm SCMI protocol, the physical clock access is at sub processor, so it needs to enable mailbox by default. Signed-off-by: Peter Chen <peter.chen@cixtech.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+)