| Message ID | Y78rn+0fVNOxHLKt@spud (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | e2f7096f1e76845cfa6e19b54f6f3674925fc28b |
| Headers | show |
| Series | [GIT,PULL] RISC-V DT for v6.2-rc4 | expand |
Hello: This pull request was applied to soc/soc.git (arm/fixes) by Arnd Bergmann <arnd@arndb.de>: On Wed, 11 Jan 2023 21:35:27 +0000 you wrote: > Hey Arnd! > > Been a quiet period since -rc1, so I only have a single DT fix for you. > Figured I'd get it out of the way & write the script that I've been > meaning to write since I sent the first pair of PRs at the same time. > Hopefully I didn't break anything in the process! > > [...] Here is the summary with links: - [GIT,PULL] RISC-V DT for v6.2-rc4 https://git.kernel.org/soc/soc/c/e2f7096f1e76 You are awesome, thank you!
Hello: This pull request was applied to soc/soc.git (for-next) by Arnd Bergmann <arnd@arndb.de>: On Wed, 11 Jan 2023 21:35:27 +0000 you wrote: > Hey Arnd! > > Been a quiet period since -rc1, so I only have a single DT fix for you. > Figured I'd get it out of the way & write the script that I've been > meaning to write since I sent the first pair of PRs at the same time. > Hopefully I didn't break anything in the process! > > [...] Here is the summary with links: - [GIT,PULL] RISC-V DT for v6.2-rc4 https://git.kernel.org/soc/soc/c/e2f7096f1e76 You are awesome, thank you!
Hey Arnd! Been a quiet period since -rc1, so I only have a single DT fix for you. Figured I'd get it out of the way & write the script that I've been meaning to write since I sent the first pair of PRs at the same time. Hopefully I didn't break anything in the process! Thanks, Conor. The following changes since commit 1b929c02afd37871d5afb9d498426f83432e71c2: Linux 6.2-rc1 (2022-12-25 13:41:39 -0800) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-dt-fixes-for-v6.2-rc4 for you to fetch changes up to 43d5f5d63699724d47f0d9e0eae516a260d232b4: riscv: dts: sifive: fu740: fix size of pcie 32bit memory (2023-01-07 19:31:37 +0000) ---------------------------------------------------------------- RISC-V DeviceTrees for v6.2 SiFive: A solitary fix for the PCI memory regions on the unmatched, triggered by an SM768. No-one must have tried one until just recently! Signed-off-by: Conor Dooley <conor.dooley@microchip.com> ---------------------------------------------------------------- Ben Dooks (1): riscv: dts: sifive: fu740: fix size of pcie 32bit memory arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)