@@ -44,6 +44,10 @@
#define DWC3_LSM_5_GBPS 5
#define DWC3_LSM_10_GBPS 10
+/* Sublink Speed Attribute ID */
+#define DWC3_SSP_SSID_GEN2 2
+#define DWC3_SSP_SSID_GEN1 1
+
#define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
#define DWC3_EVENT_BUFFERS_SIZE 4096
#define DWC3_EVENT_TYPE_MASK 0xfe
@@ -3662,6 +3662,55 @@ int dwc3_gadget_init(struct dwc3 *dwc)
dwc->revision);
dwc->gadget.max_speed = dwc->maximum_speed;
+ dwc->gadget.max_num_lanes = dwc->maximum_num_lanes;
+
+ if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
+ struct usb_sublink_speed *ssa;
+ int i;
+
+ /*
+ * Multiple sublink speeds are only available to DWC_usb32
+ * devices that can operate at gen2x2 max.
+ */
+ if (dwc->maximum_lsm == DWC3_LSM_10_GBPS &&
+ dwc->maximum_num_lanes == 2) {
+ dwc->gadget.ssac = 3;
+ dwc->gadget.min_speed_ssid = DWC3_SSP_SSID_GEN1;
+ dwc->gadget.max_speed_ssid = DWC3_SSP_SSID_GEN2;
+ } else if (dwc->maximum_lsm == DWC3_LSM_5_GBPS &&
+ dwc->maximum_num_lanes == 2) {
+ dwc->gadget.ssac = 1;
+ dwc->gadget.min_speed_ssid = DWC3_SSP_SSID_GEN1;
+ dwc->gadget.max_speed_ssid = DWC3_SSP_SSID_GEN1;
+ } else {
+ dwc->gadget.ssac = 1;
+ dwc->gadget.min_speed_ssid = DWC3_SSP_SSID_GEN2;
+ dwc->gadget.max_speed_ssid = DWC3_SSP_SSID_GEN2;
+ }
+
+ for (i = 0; i < dwc->gadget.ssac + 1; i++) {
+ ssa = &dwc->gadget.sublink_speed[i];
+
+ if (dwc->gadget.ssac > 1 && i > 1)
+ ssa->id = dwc->gadget.max_speed_ssid;
+ else
+ ssa->id = dwc->gadget.min_speed_ssid;
+
+ if (ssa->id == DWC3_SSP_SSID_GEN1)
+ ssa->mantissa = DWC3_LSM_5_GBPS;
+ else
+ ssa->mantissa = DWC3_LSM_10_GBPS;
+
+ /* First attribute is RX followed by TX */
+ if (i % 2)
+ ssa->type = USB_ST_SYMMETRIC_TX;
+ else
+ ssa->type = USB_ST_SYMMETRIC_RX;
+
+ ssa->exponent = USB_LSE_GBPS;
+ ssa->protocol = USB_LP_SSP;
+ }
+ }
/*
* REVISIT: Here we should clear all pending IRQs to be
Report the sublink speed attributes to the usb_gadget structure based on the dwc3 device capability maximum_lsm and maximum_num_lanes. Only DWC_usb32 supports 2 sublink speeds if it can operate with 2 lanes. (i.e. at SSP, it can operate as gen1x2) Note: the SSID DWC3_SSP_SSID_GEN2 and DWC3_SSP_SSID_GEN1 are arbitrary. There's no standard according to the USB 3.2 spec as long as they are unique and within 0-15. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> --- Changes in v2: - Fix missing check for gen1x2 when writing to sublink speed attributes - Minor fix in commit message (first commit sentence ended with comma) drivers/usb/dwc3/core.h | 4 ++++ drivers/usb/dwc3/gadget.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+)