| Message ID | 20231010081909.2899101-1-ping.bai@nxp.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [1/3] wdog: imx7ulp: Enable wdog int_en bit for watchdog any reset | expand |
On Tue, Oct 10, 2023 at 04:19:07PM +0800, Jacky Bai wrote: > The wdog INT_EN bit in CS register should be set to '1' to trigger > WDOG_ANY external reset on i.MX93. > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> > --- > drivers/watchdog/imx7ulp_wdt.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/watchdog/imx7ulp_wdt.c b/drivers/watchdog/imx7ulp_wdt.c > index c703586c6e5f..b21d7a74a42d 100644 > --- a/drivers/watchdog/imx7ulp_wdt.c > +++ b/drivers/watchdog/imx7ulp_wdt.c > @@ -23,6 +23,7 @@ > #define LPO_CLK_SHIFT 8 > #define WDOG_CS_CLK (LPO_CLK << LPO_CLK_SHIFT) > #define WDOG_CS_EN BIT(7) > +#define WDOG_CS_INT_EN BIT(6) > #define WDOG_CS_UPDATE BIT(5) > #define WDOG_CS_WAIT BIT(1) > #define WDOG_CS_STOP BIT(0) > @@ -62,6 +63,7 @@ struct imx7ulp_wdt_device { > void __iomem *base; > struct clk *clk; > bool post_rcs_wait; > + bool ext_reset; > const struct imx_wdt_hw_feature *hw; > }; > > @@ -285,6 +287,9 @@ static int imx7ulp_wdt_init(struct imx7ulp_wdt_device *wdt, unsigned int timeout > if (wdt->hw->prescaler_enable) > val |= WDOG_CS_PRES; > > + if (wdt->ext_reset) > + val |= WDOG_CS_INT_EN; > + > do { > ret = _imx7ulp_wdt_init(wdt, timeout, val); > toval = readl(wdt->base + WDOG_TOVAL); > @@ -321,6 +326,9 @@ static int imx7ulp_wdt_probe(struct platform_device *pdev) > return PTR_ERR(imx7ulp_wdt->clk); > } > > + /* The WDOG may need to do external reset through dedicated pin */ > + imx7ulp_wdt->ext_reset = of_property_read_bool(dev->of_node, "fsl,ext-reset-output"); > + > imx7ulp_wdt->post_rcs_wait = true; > if (of_device_is_compatible(dev->of_node, > "fsl,imx8ulp-wdt")) { > -- > 2.34.1 >
diff --git a/drivers/watchdog/imx7ulp_wdt.c b/drivers/watchdog/imx7ulp_wdt.c index c703586c6e5f..b21d7a74a42d 100644 --- a/drivers/watchdog/imx7ulp_wdt.c +++ b/drivers/watchdog/imx7ulp_wdt.c @@ -23,6 +23,7 @@ #define LPO_CLK_SHIFT 8 #define WDOG_CS_CLK (LPO_CLK << LPO_CLK_SHIFT) #define WDOG_CS_EN BIT(7) +#define WDOG_CS_INT_EN BIT(6) #define WDOG_CS_UPDATE BIT(5) #define WDOG_CS_WAIT BIT(1) #define WDOG_CS_STOP BIT(0) @@ -62,6 +63,7 @@ struct imx7ulp_wdt_device { void __iomem *base; struct clk *clk; bool post_rcs_wait; + bool ext_reset; const struct imx_wdt_hw_feature *hw; }; @@ -285,6 +287,9 @@ static int imx7ulp_wdt_init(struct imx7ulp_wdt_device *wdt, unsigned int timeout if (wdt->hw->prescaler_enable) val |= WDOG_CS_PRES; + if (wdt->ext_reset) + val |= WDOG_CS_INT_EN; + do { ret = _imx7ulp_wdt_init(wdt, timeout, val); toval = readl(wdt->base + WDOG_TOVAL); @@ -321,6 +326,9 @@ static int imx7ulp_wdt_probe(struct platform_device *pdev) return PTR_ERR(imx7ulp_wdt->clk); } + /* The WDOG may need to do external reset through dedicated pin */ + imx7ulp_wdt->ext_reset = of_property_read_bool(dev->of_node, "fsl,ext-reset-output"); + imx7ulp_wdt->post_rcs_wait = true; if (of_device_is_compatible(dev->of_node, "fsl,imx8ulp-wdt")) {