@@ -701,7 +701,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
- udelay(100);
+ udelay(1000);
REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
@@ -713,7 +713,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c);
- udelay(110);
+ udelay(1000);
}
pll = ath9k_hw_compute_pll_control(ah, chan);