Message ID | 1607609124-17250-6-git-send-email-kvalo@codeaurora.org (mailing list archive) |
---|---|
State | Accepted |
Commit | 0ccdf43988279eed70dece82ffff08fb15278d2c |
Delegated to: | Kalle Valo |
Headers | show |
Series | ath11k: QCA6390 stability fixes | expand |
On 12/10/20 6:05 AM, Kalle Valo wrote: > From: Carl Huang <cjhuang@codeaurora.org> > > It's recommended to disable VDD4BLOW during initialisation. Can you explain more about "recommended by whom and why"? Thanks, Peter
Peter Oh <peter.oh@eero.com> writes: > On 12/10/20 6:05 AM, Kalle Valo wrote: >> From: Carl Huang <cjhuang@codeaurora.org> >> >> It's recommended to disable VDD4BLOW during initialisation. > > Can you explain more about "recommended by whom and why"? It's coming from the internal teams, I understood the internal driver does the same.
diff --git a/drivers/net/wireless/ath/ath11k/pci.c b/drivers/net/wireless/ath/ath11k/pci.c index 064c35052697..818e37c32a85 100644 --- a/drivers/net/wireless/ath/ath11k/pci.c +++ b/drivers/net/wireless/ath/ath11k/pci.c @@ -346,6 +346,15 @@ static void ath11k_pci_clear_all_intrs(struct ath11k_base *ab) ath11k_pci_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL); } +static void ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base *ab) +{ + u32 val; + + val = ath11k_pci_read32(ab, WLAON_QFPROM_PWR_CTRL_REG); + val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK; + ath11k_pci_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val); +} + static void ath11k_pci_force_wake(struct ath11k_base *ab) { ath11k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1); @@ -357,6 +366,7 @@ static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on) if (power_on) { ath11k_pci_enable_ltssm(ab); ath11k_pci_clear_all_intrs(ab); + ath11k_pci_set_wlaon_pwr_ctrl(ab); ath11k_pci_fix_l1ss(ab); } diff --git a/drivers/net/wireless/ath/ath11k/pci.h b/drivers/net/wireless/ath/ath11k/pci.h index 6e7cc8904c3d..0432a702416b 100644 --- a/drivers/net/wireless/ath/ath11k/pci.h +++ b/drivers/net/wireless/ath/ath11k/pci.h @@ -45,6 +45,9 @@ #define PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG4_VAL 0xff #define PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG_MSK 0x000000ff +#define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c +#define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4 + struct ath11k_msi_user { char *name; int num_vectors;