[V2,15/18] rtw89: 8852a: add 8852a RFK tables

Message ID	20210104092036.16089-13-pkshih@realtek.com (mailing list archive)
State	Superseded
Delegated to:	Kalle Valo
Headers	show Return-Path: <linux-wireless-owner@kernel.org> Authenticated-By: X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 1049LZ650024469, This message is accepted by code: ctloc85258 From: Ping-Ke Shih <pkshih@realtek.com> To: <kvalo@codeaurora.org> CC: <linux-wireless@vger.kernel.org> Subject: [PATCH V2 15/18] rtw89: 8852a: add 8852a RFK tables Date: Mon, 4 Jan 2021 17:20:33 +0800 Message-ID: <20210104092036.16089-13-pkshih@realtek.com> In-Reply-To: <20210104092036.16089-1-pkshih@realtek.com> References: <20210104092036.16089-1-pkshih@realtek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII Precedence: bulk
Series	rtw89: add Realtek 802.11ax driver \| expand [V2,00/18] rtw89: add Realtek 802.11ax driver [V2,01/18] rtw89: add CAM files [V2,02/18] rtw89: add BT coexistence files [V2,03/18] rtw89: add core and trx files [V2,04/18] rtw89: add debug files [V2,05/18] rtw89: add efuse files [V2,06/18] rtw89: add files to download and communicate with firmware [V2,07/18] rtw89: add MAC files [V2,08/18] rtw89: implement mac80211 ops [V2,09/18] rtw89: add pci files [V2,10/18] rtw89: add phy files [V2,11/18] rtw89: define register names [V2,12/18] rtw89: add regulatory support [V2,13/18] rtw89: 8852a: add 8852a specific files [V2,14/18] rtw89: 8852a: add 8852a RFK files [V2,15/18] rtw89: 8852a: add 8852a RFK tables [V2,16/18] rtw89: 8852a: add 8852a tables [V2,17/18] rtw89: add ser to recover error reported by firmware [V2,18/18] rtw89: add Kconfig and Makefile

diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.c b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.c new file mode 100644 index 000000000000..78a757b56e07 --- /dev/null +++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.c @@ -0,0 +1,1561 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* Copyright(c) 2019-2020 Realtek Corporation + */ + +#include "rtw8852a_rfk_table.h" + +static const struct rtw89_reg5_def rtw8852a_tssi_sys_defs[] = { + DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001), + DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002), + DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001), + DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002), + DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005), + DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005), + DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005), + DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005), + DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033), + DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033), + DECL_RFK_WM(0x32bc, 0x000000f0, 0x00000005), + DECL_RFK_WM(0x32bc, 0x00000f00, 0x00000005), + DECL_RFK_WM(0x32bc, 0x000f0000, 0x00000005), + DECL_RFK_WM(0x32bc, 0x0000f000, 0x00000005), + DECL_RFK_WM(0x320c, 0x000000ff, 0x00000033), + DECL_RFK_WM(0x32c0, 0x0ff00000, 0x00000033), + DECL_RFK_WM(0x0300, 0xff000000, 0x00000019), + DECL_RFK_WM(0x0304, 0x000000ff, 0x00000019), + DECL_RFK_WM(0x0304, 0x0000ff00, 0x0000001d), + DECL_RFK_WM(0x0314, 0xffff0000, 0x00002044), + DECL_RFK_WM(0x0318, 0x0000ffff, 0x00002042), + DECL_RFK_WM(0x0318, 0xffff0000, 0x00002002), + DECL_RFK_WM(0x0020, 0x0000ffff, 0x0000ef81), + DECL_RFK_WM(0x0024, 0x0000ffff, 0x0000ef81), + DECL_RFK_WM(0x0704, 0xffff0000, 0x0000601e), + DECL_RFK_WM(0x2704, 0xffff0000, 0x0000601e), + DECL_RFK_WM(0x0700, 0xf0000000, 0x00000004), + DECL_RFK_WM(0x2700, 0xf0000000, 0x00000004), + DECL_RFK_WM(0x0650, 0x3c000000, 0x00000000), + DECL_RFK_WM(0x2650, 0x3c000000, 0x00000000), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_sys_defs); + +static const struct rtw89_reg5_def rtw8852a_tssi_sys_defs_2g[] = { + DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033), + DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033), + DECL_RFK_WM(0x320c, 0x0ff00000, 0x00000033), + DECL_RFK_WM(0x320c, 0x000000ff, 0x00000033), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_sys_defs_2g); + +static const struct rtw89_reg5_def rtw8852a_tssi_sys_defs_5g[] = { + DECL_RFK_WM(0x120c, 0x000000ff, 0x00000044), + DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000044), + DECL_RFK_WM(0x32c0, 0x0ff00000, 0x00000044), + DECL_RFK_WM(0x320c, 0x000000ff, 0x00000044), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_sys_defs_5g); + +static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_defs_a[] = { + DECL_RFK_WM(0x5800, 0x000000ff, 0x0000007f), + DECL_RFK_WM(0x5800, 0x0000ff00, 0x00000080), + DECL_RFK_WM(0x5800, 0x003f0000, 0x0000003f), + DECL_RFK_WM(0x5800, 0x0fc00000, 0x00000000), + DECL_RFK_WM(0x5800, 0x10000000, 0x00000000), + DECL_RFK_WM(0x5800, 0x20000000, 0x00000000), + DECL_RFK_WM(0x5800, 0xc0000000, 0x00000000), + DECL_RFK_WM(0x5804, 0xf8000000, 0x00000000), + DECL_RFK_WM(0x580c, 0x0000007f, 0x00000040), + DECL_RFK_WM(0x580c, 0x00007f00, 0x00000040), + DECL_RFK_WM(0x580c, 0x00008000, 0x00000000), + DECL_RFK_WM(0x580c, 0x0fff0000, 0x00000000), + DECL_RFK_WM(0x5810, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x5810, 0x00000200, 0x00000000), + DECL_RFK_WM(0x5810, 0x0000fc00, 0x00000000), + DECL_RFK_WM(0x5810, 0x00010000, 0x00000001), + DECL_RFK_WM(0x5810, 0x00fe0000, 0x00000000), + DECL_RFK_WM(0x5810, 0x01000000, 0x00000001), + DECL_RFK_WM(0x5810, 0x06000000, 0x00000000), + DECL_RFK_WM(0x5810, 0x38000000, 0x00000003), + DECL_RFK_WM(0x5810, 0x40000000, 0x00000001), + DECL_RFK_WM(0x5810, 0x80000000, 0x00000000), + DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x5814, 0x00000c00, 0x00000000), + DECL_RFK_WM(0x5814, 0x00001000, 0x00000001), + DECL_RFK_WM(0x5814, 0x00002000, 0x00000000), + DECL_RFK_WM(0x5814, 0x00004000, 0x00000001), + DECL_RFK_WM(0x5814, 0x00038000, 0x00000005), + DECL_RFK_WM(0x5814, 0x003c0000, 0x00000000), + DECL_RFK_WM(0x5814, 0x01c00000, 0x00000000), + DECL_RFK_WM(0x5814, 0x18000000, 0x00000000), + DECL_RFK_WM(0x5814, 0xe0000000, 0x00000000), + DECL_RFK_WM(0x5818, 0x000000ff, 0x00000000), + DECL_RFK_WM(0x5818, 0x0001ff00, 0x00000018), + DECL_RFK_WM(0x5818, 0x03fe0000, 0x00000016), + DECL_RFK_WM(0x5818, 0xfc000000, 0x00000000), + DECL_RFK_WM(0x581c, 0x000003ff, 0x00000280), + DECL_RFK_WM(0x581c, 0x000ffc00, 0x00000200), + DECL_RFK_WM(0x581c, 0x00100000, 0x00000000), + DECL_RFK_WM(0x581c, 0x01e00000, 0x00000008), + DECL_RFK_WM(0x581c, 0x01e00000, 0x0000000e), + DECL_RFK_WM(0x581c, 0x1e000000, 0x00000008), + DECL_RFK_WM(0x581c, 0x1e000000, 0x0000000e), + DECL_RFK_WM(0x581c, 0x20000000, 0x00000000), + DECL_RFK_WM(0x5820, 0x00000fff, 0x00000080), + DECL_RFK_WM(0x5820, 0x0000f000, 0x0000000f), + DECL_RFK_WM(0x5820, 0x001f0000, 0x00000000), + DECL_RFK_WM(0x5820, 0xffe00000, 0x00000000), + DECL_RFK_WM(0x5824, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x5824, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x5828, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x582c, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x582c, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x5830, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x5834, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x5834, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x5838, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x583c, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x583c, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x5840, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x5844, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x5844, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x5848, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x584c, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x584c, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x5850, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x5854, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x5854, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x5858, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x585c, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x585c, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x5860, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x5828, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x5828, 0x7fc00000, 0x00000000), + DECL_RFK_WM(0x5830, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x5830, 0x7fc00000, 0x00000000), + DECL_RFK_WM(0x5838, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x5838, 0x7fc00000, 0x00000000), + DECL_RFK_WM(0x5840, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x5840, 0x7fc00000, 0x00000000), + DECL_RFK_WM(0x5848, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x5848, 0x7fc00000, 0x00000000), + DECL_RFK_WM(0x5850, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x5850, 0x7fc00000, 0x00000000), + DECL_RFK_WM(0x5858, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x5858, 0x7fc00000, 0x00000000), + DECL_RFK_WM(0x5860, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x5860, 0x7fc00000, 0x00000000), + DECL_RFK_WM(0x5860, 0x80000000, 0x00000000), + DECL_RFK_WM(0x5864, 0x000003ff, 0x000001ff), + DECL_RFK_WM(0x5864, 0x000ffc00, 0x00000200), + DECL_RFK_WM(0x5864, 0x03f00000, 0x00000000), + DECL_RFK_WM(0x5864, 0x04000000, 0x00000000), + DECL_RFK_WM(0x5898, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x589c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x58a0, 0x000000ff, 0x000000fd), + DECL_RFK_WM(0x58a0, 0x0000ff00, 0x000000e5), + DECL_RFK_WM(0x58a0, 0x00ff0000, 0x000000cd), + DECL_RFK_WM(0x58a0, 0xff000000, 0x000000b5), + DECL_RFK_WM(0x58a4, 0x000000ff, 0x00000016), + DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), + DECL_RFK_WM(0x58a4, 0x03fe0000, 0x00000000), + DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x58a8, 0x0003fe00, 0x00000000), + DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), + DECL_RFK_WM(0x58ac, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000000), + DECL_RFK_WM(0x58ac, 0x07fc0000, 0x00000000), + DECL_RFK_WM(0x58b0, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x58b4, 0x0000001f, 0x00000000), + DECL_RFK_WM(0x58b4, 0x00000020, 0x00000000), + DECL_RFK_WM(0x58b4, 0x000001c0, 0x00000000), + DECL_RFK_WM(0x58b4, 0x00000200, 0x00000000), + DECL_RFK_WM(0x58b4, 0x0000f000, 0x00000002), + DECL_RFK_WM(0x58b4, 0x00ff0000, 0x00000000), + DECL_RFK_WM(0x58b4, 0x7f000000, 0x0000000a), + DECL_RFK_WM(0x58b8, 0x0000007f, 0x00000028), + DECL_RFK_WM(0x58b8, 0x00007f00, 0x00000076), + DECL_RFK_WM(0x58b8, 0x007f0000, 0x00000000), + DECL_RFK_WM(0x58b8, 0x7f000000, 0x00000000), + DECL_RFK_WM(0x58bc, 0x000000ff, 0x0000007f), + DECL_RFK_WM(0x58bc, 0x0000ff00, 0x00000080), + DECL_RFK_WM(0x58bc, 0x00030000, 0x00000003), + DECL_RFK_WM(0x58bc, 0x000c0000, 0x00000001), + DECL_RFK_WM(0x58bc, 0x00300000, 0x00000003), + DECL_RFK_WM(0x58bc, 0x00c00000, 0x00000003), + DECL_RFK_WM(0x58bc, 0x07000000, 0x00000007), + DECL_RFK_WM(0x58c0, 0x00fe0000, 0x0000007f), + DECL_RFK_WM(0x58c0, 0xff000000, 0x00000000), + DECL_RFK_WM(0x58c4, 0x0003ffff, 0x0003ffff), + DECL_RFK_WM(0x58c4, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x58c4, 0xc0000000, 0x00000000), + DECL_RFK_WM(0x58c8, 0x00ffffff, 0x00000000), + DECL_RFK_WM(0x58c8, 0xf0000000, 0x00000000), + DECL_RFK_WM(0x58cc, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x58d0, 0x00001fff, 0x00000101), + DECL_RFK_WM(0x58d0, 0x0001e000, 0x00000004), + DECL_RFK_WM(0x58d0, 0x03fe0000, 0x00000100), + DECL_RFK_WM(0x58d0, 0x04000000, 0x00000000), + DECL_RFK_WM(0x58d4, 0x000000ff, 0x00000000), + DECL_RFK_WM(0x58d4, 0x0003fe00, 0x000000ff), + DECL_RFK_WM(0x58d4, 0x07fc0000, 0x00000100), + DECL_RFK_WM(0x58d8, 0x000001ff, 0x0000016c), + DECL_RFK_WM(0x58d8, 0x0003fe00, 0x0000005c), + DECL_RFK_WM(0x58d8, 0x000c0000, 0x00000002), + DECL_RFK_WM(0x58d8, 0xfff00000, 0x00000800), + DECL_RFK_WM(0x58dc, 0x000000ff, 0x0000007f), + DECL_RFK_WM(0x58dc, 0x0000ff00, 0x00000080), + DECL_RFK_WM(0x58dc, 0x00010000, 0x00000000), + DECL_RFK_WM(0x58dc, 0x3ff00000, 0x00000000), + DECL_RFK_WM(0x58dc, 0xc0000000, 0x00000002), + DECL_RFK_WM(0x58f0, 0x000001ff, 0x000001ff), + DECL_RFK_WM(0x58f0, 0x0003fe00, 0x00000000), + DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_defs_a); + +static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_defs_b[] = { + DECL_RFK_WM(0x7800, 0x000000ff, 0x0000007f), + DECL_RFK_WM(0x7800, 0x0000ff00, 0x00000080), + DECL_RFK_WM(0x7800, 0x003f0000, 0x0000003f), + DECL_RFK_WM(0x7800, 0x0fc00000, 0x00000000), + DECL_RFK_WM(0x7800, 0x10000000, 0x00000000), + DECL_RFK_WM(0x7800, 0x20000000, 0x00000000), + DECL_RFK_WM(0x7800, 0xc0000000, 0x00000000), + DECL_RFK_WM(0x7804, 0xf8000000, 0x00000000), + DECL_RFK_WM(0x780c, 0x0000007f, 0x00000040), + DECL_RFK_WM(0x780c, 0x00007f00, 0x00000040), + DECL_RFK_WM(0x780c, 0x00008000, 0x00000000), + DECL_RFK_WM(0x780c, 0x0fff0000, 0x00000000), + DECL_RFK_WM(0x7810, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x7810, 0x00000200, 0x00000000), + DECL_RFK_WM(0x7810, 0x0000fc00, 0x00000000), + DECL_RFK_WM(0x7810, 0x00010000, 0x00000001), + DECL_RFK_WM(0x7810, 0x00fe0000, 0x00000000), + DECL_RFK_WM(0x7810, 0x01000000, 0x00000001), + DECL_RFK_WM(0x7810, 0x06000000, 0x00000000), + DECL_RFK_WM(0x7810, 0x38000000, 0x00000003), + DECL_RFK_WM(0x7810, 0x40000000, 0x00000001), + DECL_RFK_WM(0x7810, 0x80000000, 0x00000000), + DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x7814, 0x00000c00, 0x00000000), + DECL_RFK_WM(0x7814, 0x00001000, 0x00000001), + DECL_RFK_WM(0x7814, 0x00002000, 0x00000000), + DECL_RFK_WM(0x7814, 0x00004000, 0x00000001), + DECL_RFK_WM(0x7814, 0x00038000, 0x00000005), + DECL_RFK_WM(0x7814, 0x003c0000, 0x00000000), + DECL_RFK_WM(0x7814, 0x01c00000, 0x00000000), + DECL_RFK_WM(0x7814, 0x18000000, 0x00000000), + DECL_RFK_WM(0x7814, 0xe0000000, 0x00000000), + DECL_RFK_WM(0x7818, 0x000000ff, 0x00000000), + DECL_RFK_WM(0x7818, 0x0001ff00, 0x00000018), + DECL_RFK_WM(0x7818, 0x03fe0000, 0x00000016), + DECL_RFK_WM(0x7818, 0xfc000000, 0x00000000), + DECL_RFK_WM(0x781c, 0x000003ff, 0x00000280), + DECL_RFK_WM(0x781c, 0x000ffc00, 0x00000200), + DECL_RFK_WM(0x781c, 0x00100000, 0x00000000), + DECL_RFK_WM(0x781c, 0x01e00000, 0x00000008), + DECL_RFK_WM(0x781c, 0x01e00000, 0x0000000e), + DECL_RFK_WM(0x781c, 0x1e000000, 0x00000008), + DECL_RFK_WM(0x781c, 0x1e000000, 0x0000000e), + DECL_RFK_WM(0x781c, 0x20000000, 0x00000000), + DECL_RFK_WM(0x7820, 0x00000fff, 0x00000080), + DECL_RFK_WM(0x7820, 0x0000f000, 0x00000000), + DECL_RFK_WM(0x7820, 0x001f0000, 0x00000000), + DECL_RFK_WM(0x7820, 0xffe00000, 0x00000000), + DECL_RFK_WM(0x7824, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x7824, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x7828, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x782c, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x782c, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x7830, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x7834, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x7834, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x7838, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x783c, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x783c, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x7840, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x7844, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x7844, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x7848, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x784c, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x784c, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x7850, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x7854, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x7854, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x7858, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x785c, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x785c, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x7860, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x7828, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x7828, 0x7fc00000, 0x00000000), + DECL_RFK_WM(0x7830, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x7830, 0x7fc00000, 0x00000000), + DECL_RFK_WM(0x7838, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x7838, 0x7fc00000, 0x00000000), + DECL_RFK_WM(0x7840, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x7840, 0x7fc00000, 0x00000000), + DECL_RFK_WM(0x7848, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x7848, 0x7fc00000, 0x00000000), + DECL_RFK_WM(0x7850, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x7850, 0x7fc00000, 0x00000000), + DECL_RFK_WM(0x7858, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x7858, 0x7fc00000, 0x00000000), + DECL_RFK_WM(0x7860, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x7860, 0x7fc00000, 0x00000000), + DECL_RFK_WM(0x7860, 0x80000000, 0x00000000), + DECL_RFK_WM(0x7864, 0x000003ff, 0x000001ff), + DECL_RFK_WM(0x7864, 0x000ffc00, 0x00000200), + DECL_RFK_WM(0x7864, 0x03f00000, 0x00000000), + DECL_RFK_WM(0x7864, 0x04000000, 0x00000000), + DECL_RFK_WM(0x7898, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x789c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x78a0, 0x000000ff, 0x000000fd), + DECL_RFK_WM(0x78a0, 0x0000ff00, 0x000000e5), + DECL_RFK_WM(0x78a0, 0x00ff0000, 0x000000cd), + DECL_RFK_WM(0x78a0, 0xff000000, 0x000000b5), + DECL_RFK_WM(0x78a4, 0x000000ff, 0x00000016), + DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), + DECL_RFK_WM(0x78a4, 0x03fe0000, 0x00000000), + DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x78a8, 0x0003fe00, 0x00000000), + DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), + DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x78ac, 0x0003fe00, 0x00000000), + DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000000), + DECL_RFK_WM(0x78b0, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x78b4, 0x0000001f, 0x00000000), + DECL_RFK_WM(0x78b4, 0x00000020, 0x00000000), + DECL_RFK_WM(0x78b4, 0x000001c0, 0x00000000), + DECL_RFK_WM(0x78b4, 0x00000200, 0x00000000), + DECL_RFK_WM(0x78b4, 0x0000f000, 0x00000002), + DECL_RFK_WM(0x78b4, 0x00ff0000, 0x00000000), + DECL_RFK_WM(0x78b4, 0x7f000000, 0x0000000a), + DECL_RFK_WM(0x78b8, 0x0000007f, 0x00000028), + DECL_RFK_WM(0x78b8, 0x00007f00, 0x00000076), + DECL_RFK_WM(0x78b8, 0x007f0000, 0x00000000), + DECL_RFK_WM(0x78b8, 0x7f000000, 0x00000000), + DECL_RFK_WM(0x78bc, 0x000000ff, 0x0000007f), + DECL_RFK_WM(0x78bc, 0x0000ff00, 0x00000080), + DECL_RFK_WM(0x78bc, 0x00030000, 0x00000003), + DECL_RFK_WM(0x78bc, 0x000c0000, 0x00000001), + DECL_RFK_WM(0x78bc, 0x00300000, 0x00000003), + DECL_RFK_WM(0x78bc, 0x00c00000, 0x00000003), + DECL_RFK_WM(0x78bc, 0x07000000, 0x00000007), + DECL_RFK_WM(0x78c0, 0x00fe0000, 0x0000007f), + DECL_RFK_WM(0x78c0, 0xff000000, 0x00000000), + DECL_RFK_WM(0x78c4, 0x0003ffff, 0x0003ffff), + DECL_RFK_WM(0x78c4, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x78c4, 0xc0000000, 0x00000000), + DECL_RFK_WM(0x78c8, 0x00ffffff, 0x00000000), + DECL_RFK_WM(0x78c8, 0xf0000000, 0x00000000), + DECL_RFK_WM(0x78cc, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x78d0, 0x00001fff, 0x00000101), + DECL_RFK_WM(0x78d0, 0x0001e000, 0x00000004), + DECL_RFK_WM(0x78d0, 0x03fe0000, 0x00000100), + DECL_RFK_WM(0x78d0, 0x04000000, 0x00000000), + DECL_RFK_WM(0x78d4, 0x000000ff, 0x00000000), + DECL_RFK_WM(0x78d4, 0x0003fe00, 0x000000ff), + DECL_RFK_WM(0x78d4, 0x07fc0000, 0x00000100), + DECL_RFK_WM(0x78d8, 0x000001ff, 0x0000016c), + DECL_RFK_WM(0x78d8, 0x0003fe00, 0x0000005c), + DECL_RFK_WM(0x78d8, 0x000c0000, 0x00000002), + DECL_RFK_WM(0x78d8, 0xfff00000, 0x00000800), + DECL_RFK_WM(0x78dc, 0x000000ff, 0x0000007f), + DECL_RFK_WM(0x78dc, 0x0000ff00, 0x00000080), + DECL_RFK_WM(0x78dc, 0x00010000, 0x00000000), + DECL_RFK_WM(0x78dc, 0x3ff00000, 0x00000000), + DECL_RFK_WM(0x78dc, 0xc0000000, 0x00000002), + DECL_RFK_WM(0x78f0, 0x000001ff, 0x000001ff), + DECL_RFK_WM(0x78f0, 0x0003fe00, 0x00000000), + DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_defs_b); + +static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_a[] = { + DECL_RFK_WM(0x58a0, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x58e4, 0x0000007f, 0x00000020), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_a); + +static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_b[] = { + DECL_RFK_WM(0x78a0, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x78e4, 0x0000007f, 0x00000020), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_b); + +static const struct rtw89_reg5_def rtw8852a_tssi_dck_defs_a[] = { + DECL_RFK_WM(0x580c, 0x0fff0000, 0x00000000), + DECL_RFK_WM(0x5814, 0x00001000, 0x00000001), + DECL_RFK_WM(0x5814, 0x00002000, 0x00000001), + DECL_RFK_WM(0x5814, 0x00004000, 0x00000001), + DECL_RFK_WM(0x5814, 0x00038000, 0x00000005), + DECL_RFK_WM(0x5814, 0x003c0000, 0x00000003), + DECL_RFK_WM(0x5814, 0x18000000, 0x00000000), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_dck_defs_a); + +static const struct rtw89_reg5_def rtw8852a_tssi_dck_defs_b[] = { + DECL_RFK_WM(0x780c, 0x0fff0000, 0x00000000), + DECL_RFK_WM(0x7814, 0x00001000, 0x00000001), + DECL_RFK_WM(0x7814, 0x00002000, 0x00000001), + DECL_RFK_WM(0x7814, 0x00004000, 0x00000001), + DECL_RFK_WM(0x7814, 0x00038000, 0x00000005), + DECL_RFK_WM(0x7814, 0x003c0000, 0x00000003), + DECL_RFK_WM(0x7814, 0x18000000, 0x00000000), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_dck_defs_b); + +static const struct rtw89_reg5_def rtw8852a_tssi_dac_gain_tbl_defs_a[] = { + DECL_RFK_WM(0x58b0, 0x00000fff, 0x00000000), + DECL_RFK_WM(0x58b0, 0x00000800, 0x00000001), + DECL_RFK_WM(0x5a00, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a04, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a08, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a0c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a10, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a14, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a18, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a1c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a20, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a24, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a28, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a2c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a30, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a34, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a38, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a3c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a40, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a44, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a48, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a4c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a50, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a54, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a58, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a5c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a60, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a64, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a68, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a6c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a70, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a74, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a78, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a7c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a80, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a84, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a88, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a8c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a90, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a94, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a98, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5a9c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5aa0, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5aa4, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5aa8, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5aac, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5ab0, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5ab4, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5ab8, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5abc, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x5ac0, 0xffffffff, 0x00000000), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_dac_gain_tbl_defs_a); + +static const struct rtw89_reg5_def rtw8852a_tssi_dac_gain_tbl_defs_b[] = { + DECL_RFK_WM(0x78b0, 0x00000fff, 0x00000000), + DECL_RFK_WM(0x78b0, 0x00000800, 0x00000001), + DECL_RFK_WM(0x7a00, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a04, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a08, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a0c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a10, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a14, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a18, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a1c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a20, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a24, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a28, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a2c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a30, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a34, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a38, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a3c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a40, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a44, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a48, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a4c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a50, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a54, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a58, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a5c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a60, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a64, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a68, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a6c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a70, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a74, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a78, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a7c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a80, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a84, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a88, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a8c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a90, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a94, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a98, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7a9c, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7aa0, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7aa4, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7aa8, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7aac, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7ab0, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7ab4, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7ab8, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7abc, 0xffffffff, 0x00000000), + DECL_RFK_WM(0x7ac0, 0xffffffff, 0x00000000), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_dac_gain_tbl_defs_b); + +static const struct rtw89_reg5_def rtw8852a_tssi_slope_cal_org_defs_a[] = { + DECL_RFK_WM(0x581c, 0x00100000, 0x00000000), + DECL_RFK_WM(0x58cc, 0x00001000, 0x00000001), + DECL_RFK_WM(0x58cc, 0x00000007, 0x00000000), + DECL_RFK_WM(0x58cc, 0x00000038, 0x00000001), + DECL_RFK_WM(0x58cc, 0x000001c0, 0x00000002), + DECL_RFK_WM(0x58cc, 0x00000e00, 0x00000003), + DECL_RFK_WM(0x5828, 0x7fc00000, 0x00000040), + DECL_RFK_WM(0x5898, 0x000000ff, 0x00000040), + DECL_RFK_WM(0x5830, 0x7fc00000, 0x00000040), + DECL_RFK_WM(0x5898, 0x0000ff00, 0x00000040), + DECL_RFK_WM(0x5838, 0x7fc00000, 0x00000040), + DECL_RFK_WM(0x5898, 0x00ff0000, 0x00000040), + DECL_RFK_WM(0x5840, 0x7fc00000, 0x00000040), + DECL_RFK_WM(0x5898, 0xff000000, 0x00000040), + DECL_RFK_WM(0x5848, 0x7fc00000, 0x00000040), + DECL_RFK_WM(0x589c, 0x000000ff, 0x00000040), + DECL_RFK_WM(0x5850, 0x7fc00000, 0x00000040), + DECL_RFK_WM(0x589c, 0x0000ff00, 0x00000040), + DECL_RFK_WM(0x5858, 0x7fc00000, 0x00000040), + DECL_RFK_WM(0x589c, 0x00ff0000, 0x00000040), + DECL_RFK_WM(0x5860, 0x7fc00000, 0x00000040), + DECL_RFK_WM(0x589c, 0xff000000, 0x00000040), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_slope_cal_org_defs_a); + +static const struct rtw89_reg5_def rtw8852a_tssi_slope_cal_org_defs_b[] = { + DECL_RFK_WM(0x781c, 0x00100000, 0x00000000), + DECL_RFK_WM(0x78cc, 0x00001000, 0x00000001), + DECL_RFK_WM(0x78cc, 0x00000007, 0x00000000), + DECL_RFK_WM(0x78cc, 0x00000038, 0x00000001), + DECL_RFK_WM(0x78cc, 0x000001c0, 0x00000002), + DECL_RFK_WM(0x78cc, 0x00000e00, 0x00000003), + DECL_RFK_WM(0x7828, 0x7fc00000, 0x00000040), + DECL_RFK_WM(0x7898, 0x000000ff, 0x00000040), + DECL_RFK_WM(0x7830, 0x7fc00000, 0x00000040), + DECL_RFK_WM(0x7898, 0x0000ff00, 0x00000040), + DECL_RFK_WM(0x7838, 0x7fc00000, 0x00000040), + DECL_RFK_WM(0x7898, 0x00ff0000, 0x00000040), + DECL_RFK_WM(0x7840, 0x7fc00000, 0x00000040), + DECL_RFK_WM(0x7898, 0xff000000, 0x00000040), + DECL_RFK_WM(0x7848, 0x7fc00000, 0x00000040), + DECL_RFK_WM(0x789c, 0x000000ff, 0x00000040), + DECL_RFK_WM(0x7850, 0x7fc00000, 0x00000040), + DECL_RFK_WM(0x789c, 0x0000ff00, 0x00000040), + DECL_RFK_WM(0x7878, 0x7fc00000, 0x00000040), + DECL_RFK_WM(0x789c, 0x00ff0000, 0x00000040), + DECL_RFK_WM(0x7860, 0x7fc00000, 0x00000040), + DECL_RFK_WM(0x789c, 0xff000000, 0x00000040), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_slope_cal_org_defs_b); + +static const struct rtw89_reg5_def rtw8852a_tssi_rf_gap_tbl_defs_a[] = { + DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x58f8, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x58f8, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), + DECL_RFK_WM(0x58a4, 0x03fe0000, 0x00000000), + DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x58a8, 0x0003fe00, 0x00000000), + DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), + DECL_RFK_WM(0x58ac, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000000), + DECL_RFK_WM(0x58ac, 0x07fc0000, 0x00000000), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_rf_gap_tbl_defs_a); + +static const struct rtw89_reg5_def rtw8852a_tssi_rf_gap_tbl_defs_b[] = { + DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x78f8, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x78f8, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), + DECL_RFK_WM(0x78a4, 0x03fe0000, 0x00000000), + DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x78a8, 0x0003fe00, 0x00000000), + DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), + DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x78ac, 0x0003fe00, 0x00000000), + DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000000), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_rf_gap_tbl_defs_b); + +static const struct rtw89_reg5_def rtw8852a_tssi_slope_defs_a[] = { + DECL_RFK_WM(0x5820, 0x80000000, 0x00000000), + DECL_RFK_WM(0x5818, 0x10000000, 0x00000000), + DECL_RFK_WM(0x5814, 0x00000800, 0x00000001), + DECL_RFK_WM(0x581c, 0x20000000, 0x00000001), + DECL_RFK_WM(0x5820, 0x0000f000, 0x00000001), + DECL_RFK_WM(0x581c, 0x000003ff, 0x00000280), + DECL_RFK_WM(0x581c, 0x000ffc00, 0x00000200), + DECL_RFK_WM(0x58b8, 0x007f0000, 0x00000000), + DECL_RFK_WM(0x58b8, 0x7f000000, 0x00000000), + DECL_RFK_WM(0x58b4, 0x7f000000, 0x0000000a), + DECL_RFK_WM(0x58b8, 0x0000007f, 0x00000028), + DECL_RFK_WM(0x58b8, 0x00007f00, 0x00000076), + DECL_RFK_WM(0x5810, 0x20000000, 0x00000000), + DECL_RFK_WM(0x5814, 0x20000000, 0x00000001), + DECL_RFK_WM(0x580c, 0x10000000, 0x00000001), + DECL_RFK_WM(0x580c, 0x40000000, 0x00000001), + DECL_RFK_WM(0x5838, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x5858, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x5834, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x5834, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x5838, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x5854, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x5854, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x5858, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x5824, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x5824, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x5828, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x582c, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x582c, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x5830, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x583c, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x583c, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x5840, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x5844, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x5844, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x5848, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x584c, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x584c, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x5850, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x585c, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x585c, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x5860, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x5828, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x5830, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x5840, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x5848, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x5850, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x5860, 0x003ff000, 0x00000000), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_slope_defs_a); + +static const struct rtw89_reg5_def rtw8852a_tssi_slope_defs_b[] = { + DECL_RFK_WM(0x7820, 0x80000000, 0x00000000), + DECL_RFK_WM(0x7818, 0x10000000, 0x00000000), + DECL_RFK_WM(0x7814, 0x00000800, 0x00000001), + DECL_RFK_WM(0x781c, 0x20000000, 0x00000001), + DECL_RFK_WM(0x7820, 0x0000f000, 0x00000001), + DECL_RFK_WM(0x781c, 0x000003ff, 0x00000280), + DECL_RFK_WM(0x781c, 0x000ffc00, 0x00000200), + DECL_RFK_WM(0x78b8, 0x007f0000, 0x00000000), + DECL_RFK_WM(0x78b8, 0x7f000000, 0x00000000), + DECL_RFK_WM(0x78b4, 0x7f000000, 0x0000000a), + DECL_RFK_WM(0x78b8, 0x0000007f, 0x00000028), + DECL_RFK_WM(0x78b8, 0x00007f00, 0x00000076), + DECL_RFK_WM(0x7810, 0x20000000, 0x00000000), + DECL_RFK_WM(0x7814, 0x20000000, 0x00000001), + DECL_RFK_WM(0x780c, 0x10000000, 0x00000001), + DECL_RFK_WM(0x780c, 0x40000000, 0x00000001), + DECL_RFK_WM(0x7838, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x7858, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x7834, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x7834, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x7838, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x7854, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x7854, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x7858, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x7824, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x7824, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x7828, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x782c, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x782c, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x7830, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x783c, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x783c, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x7840, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x7844, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x7844, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x7848, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x784c, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x784c, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x7850, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x785c, 0x0003ffff, 0x000115f2), + DECL_RFK_WM(0x785c, 0x3ffc0000, 0x00000000), + DECL_RFK_WM(0x7860, 0x00000fff, 0x00000121), + DECL_RFK_WM(0x7828, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x7830, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x7840, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x7848, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x7850, 0x003ff000, 0x00000000), + DECL_RFK_WM(0x7860, 0x003ff000, 0x00000000), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_slope_defs_b); + +static const struct rtw89_reg5_def rtw8852a_tssi_track_defs_a[] = { + DECL_RFK_WM(0x5820, 0x80000000, 0x00000000), + DECL_RFK_WM(0x5818, 0x18000000, 0x00000000), + DECL_RFK_WM(0x5814, 0x00000800, 0x00000000), + DECL_RFK_WM(0x581c, 0x20000000, 0x00000001), + DECL_RFK_WM(0x5864, 0x000003ff, 0x000001ff), + DECL_RFK_WM(0x5864, 0x000ffc00, 0x00000200), + DECL_RFK_WM(0x5820, 0x00000fff, 0x00000080), + DECL_RFK_WM(0x5814, 0x01000000, 0x00000000), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_track_defs_a); + +static const struct rtw89_reg5_def rtw8852a_tssi_track_defs_b[] = { + DECL_RFK_WM(0x7820, 0x80000000, 0x00000000), + DECL_RFK_WM(0x7818, 0x18000000, 0x00000000), + DECL_RFK_WM(0x7814, 0x00000800, 0x00000000), + DECL_RFK_WM(0x781c, 0x20000000, 0x00000001), + DECL_RFK_WM(0x7864, 0x000003ff, 0x000001ff), + DECL_RFK_WM(0x7864, 0x000ffc00, 0x00000200), + DECL_RFK_WM(0x7820, 0x00000fff, 0x00000080), + DECL_RFK_WM(0x7814, 0x01000000, 0x00000000), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_track_defs_b); + +static const struct rtw89_reg5_def rtw8852a_tssi_txagc_ofst_mv_avg_defs_a[] = { + DECL_RFK_WM(0x58e4, 0x00004000, 0x00000000), + DECL_RFK_WM(0x58e4, 0x00004000, 0x00000001), + DECL_RFK_WM(0x58e4, 0x00004000, 0x00000000), + DECL_RFK_WM(0x58e4, 0x00008000, 0x00000000), + DECL_RFK_WM(0x58e4, 0x000f0000, 0x00000000), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_txagc_ofst_mv_avg_defs_a); + +static const struct rtw89_reg5_def rtw8852a_tssi_txagc_ofst_mv_avg_defs_b[] = { + DECL_RFK_WM(0x78e4, 0x00004000, 0x00000000), + DECL_RFK_WM(0x78e4, 0x00004000, 0x00000001), + DECL_RFK_WM(0x78e4, 0x00004000, 0x00000000), + DECL_RFK_WM(0x78e4, 0x00008000, 0x00000000), + DECL_RFK_WM(0x78e4, 0x000f0000, 0x00000000), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_txagc_ofst_mv_avg_defs_b); + +static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_a_2g[] = { + DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x58f8, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x58f8, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), + DECL_RFK_WM(0x58a4, 0x03fe0000, 0x000001d0), + DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x58a8, 0x0003fe00, 0x000001e8), + DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), + DECL_RFK_WM(0x58ac, 0x000001ff, 0x0000000b), + DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000000), + DECL_RFK_WM(0x58ac, 0x07fc0000, 0x00000088), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_a_2g); + +static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_a_5g_1[] = { + DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x58f8, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x58f8, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), + DECL_RFK_WM(0x58a4, 0x03fe0000, 0x000001d7), + DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x58a8, 0x0003fe00, 0x000001fb), + DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), + DECL_RFK_WM(0x58ac, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000005), + DECL_RFK_WM(0x58ac, 0x07fc0000, 0x0000007c), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_a_5g_1); + +static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_a_5g_3[] = { + DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x58f8, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x58f8, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), + DECL_RFK_WM(0x58a4, 0x03fe0000, 0x000001d8), + DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x58a8, 0x0003fe00, 0x000001fc), + DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), + DECL_RFK_WM(0x58ac, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000006), + DECL_RFK_WM(0x58ac, 0x07fc0000, 0x00000078), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_a_5g_3); + +static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_a_5g_4[] = { + DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x58f8, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x58f8, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), + DECL_RFK_WM(0x58a4, 0x03fe0000, 0x000001e5), + DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x58a8, 0x0003fe00, 0x0000000a), + DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), + DECL_RFK_WM(0x58ac, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000011), + DECL_RFK_WM(0x58ac, 0x07fc0000, 0x00000075), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_a_5g_4); + +static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_b_2g[] = { + DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x78f8, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x78f8, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), + DECL_RFK_WM(0x78a4, 0x03fe0000, 0x000001cc), + DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x78a8, 0x0003fe00, 0x000001e2), + DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), + DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000005), + DECL_RFK_WM(0x78ac, 0x0003fe00, 0x00000000), + DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000089), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_b_2g); + +static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_b_5g_1[] = { + DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x78f8, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x78f8, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), + DECL_RFK_WM(0x78a4, 0x03fe0000, 0x000001d5), + DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x78a8, 0x0003fe00, 0x000001fc), + DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), + DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x78ac, 0x0003fe00, 0x00000005), + DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000079), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_b_5g_1); + +static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_b_5g_3[] = { + DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x78f8, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x78f8, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), + DECL_RFK_WM(0x78a4, 0x03fe0000, 0x000001dc), + DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x78a8, 0x0003fe00, 0x00000002), + DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), + DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x78ac, 0x0003fe00, 0x0000000b), + DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000076), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_b_5g_3); + +static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_b_5g_4[] = { + DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x78f8, 0x000003ff, 0x00000000), + DECL_RFK_WM(0x78f8, 0x000ffc00, 0x00000000), + DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), + DECL_RFK_WM(0x78a4, 0x03fe0000, 0x000001f0), + DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x78a8, 0x0003fe00, 0x00000016), + DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), + DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x78ac, 0x0003fe00, 0x0000001f), + DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000072), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_b_5g_4); + +static const struct rtw89_reg5_def rtw8852a_tssi_enable_defs_a[] = { + DECL_RFK_WRF(0x0, 0x55, 0x00080, 0x00001), + DECL_RFK_WM(0x5820, 0x80000000, 0x00000000), + DECL_RFK_WM(0x5820, 0x80000000, 0x00000001), + DECL_RFK_WM(0x5818, 0x18000000, 0x00000003), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_enable_defs_a); + +static const struct rtw89_reg5_def rtw8852a_tssi_enable_defs_b[] = { + DECL_RFK_WRF(0x1, 0x55, 0x00080, 0x00001), + DECL_RFK_WM(0x7820, 0x80000000, 0x00000000), + DECL_RFK_WM(0x7820, 0x80000000, 0x00000001), + DECL_RFK_WM(0x7818, 0x18000000, 0x00000003), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_enable_defs_b); + +static const struct rtw89_reg5_def rtw8852a_tssi_disable_defs[] = { + DECL_RFK_WM(0x5820, 0x80000000, 0x00000000), + DECL_RFK_WM(0x5818, 0x18000000, 0x00000001), + DECL_RFK_WM(0x7820, 0x80000000, 0x00000000), + DECL_RFK_WM(0x7818, 0x18000000, 0x00000001), +}; + +DECLARE_RFK_TBL(rtw8852a_tssi_disable_defs); + +static const struct rtw89_reg5_def rtw8852a_rfk_afe_init_defs[] = { + DECL_RFK_WC(0x12ec, 0x00008000), + DECL_RFK_WS(0x12ec, 0x00008000), + DECL_RFK_WC(0x5e00, 0x00000001), + DECL_RFK_WS(0x5e00, 0x00000001), + DECL_RFK_WC(0x32ec, 0x00008000), + DECL_RFK_WS(0x32ec, 0x00008000), + DECL_RFK_WC(0x7e00, 0x00000001), + DECL_RFK_WS(0x7e00, 0x00000001), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_afe_init_defs); + +static const struct rtw89_reg5_def rtw8852a_rfk_dack_reload_defs_a[] = { + DECL_RFK_WS(0x5e00, 0x00000008), + DECL_RFK_WS(0x5e50, 0x00000008), + DECL_RFK_WS(0x5e10, 0x80000000), + DECL_RFK_WS(0x5e60, 0x80000000), + DECL_RFK_WC(0x5e00, 0x00000008), + DECL_RFK_WC(0x5e50, 0x00000008), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dack_reload_defs_a); + +static const struct rtw89_reg5_def rtw8852a_rfk_dack_reload_defs_b[] = { + DECL_RFK_WS(0x7e00, 0x00000008), + DECL_RFK_WS(0x7e50, 0x00000008), + DECL_RFK_WS(0x7e10, 0x80000000), + DECL_RFK_WS(0x7e60, 0x80000000), + DECL_RFK_WC(0x7e00, 0x00000008), + DECL_RFK_WC(0x7e50, 0x00000008), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dack_reload_defs_b); + +static const struct rtw89_reg5_def rtw8852a_rfk_check_addc_defs_a[] = { + DECL_RFK_WC(0x20f4, 0x01000000), + DECL_RFK_WS(0x20f8, 0x80000000), + DECL_RFK_WM(0x20f0, 0x00ff0000, 0x00000001), + DECL_RFK_WM(0x20f0, 0x00000f00, 0x00000002), + DECL_RFK_WC(0x20f0, 0x0000000f), + DECL_RFK_WM(0x20f0, 0x000000c0, 0x00000002), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_check_addc_defs_a); + +static const struct rtw89_reg5_def rtw8852a_rfk_check_addc_defs_b[] = { + DECL_RFK_WC(0x20f4, 0x01000000), + DECL_RFK_WS(0x20f8, 0x80000000), + DECL_RFK_WM(0x20f0, 0x00ff0000, 0x00000001), + DECL_RFK_WM(0x20f0, 0x00000f00, 0x00000002), + DECL_RFK_WC(0x20f0, 0x0000000f), + DECL_RFK_WM(0x20f0, 0x000000c0, 0x00000003), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_check_addc_defs_b); + +static const struct rtw89_reg5_def rtw8852a_rfk_addck_reset_defs_a[] = { + DECL_RFK_WC(0x12d8, 0x00000030), + DECL_RFK_WC(0x32d8, 0x00000030), + DECL_RFK_WS(0x12b8, 0x40000000), + DECL_RFK_WC(0x032c, 0x40000000), + DECL_RFK_WC(0x032c, 0x00400000), + DECL_RFK_WS(0x032c, 0x00400000), + DECL_RFK_WS(0x030c, 0x0f000000), + DECL_RFK_WC(0x032c, 0x00010000), + DECL_RFK_WS(0x12dc, 0x00000002), + DECL_RFK_WM(0x030c, 0x0f000000, 0x00000003), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_addck_reset_defs_a); + +static const struct rtw89_reg5_def rtw8852a_rfk_addck_trigger_defs_a[] = { + DECL_RFK_WS(0x12d8, 0x000000c0), + DECL_RFK_WS(0x12d8, 0x00000800), + DECL_RFK_WC(0x12d8, 0x00000800), + DECL_RFK_DELAY(1), + DECL_RFK_WM(0x12d8, 0x00000300, 0x00000001), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_addck_trigger_defs_a); + +static const struct rtw89_reg5_def rtw8852a_rfk_addck_restore_defs_a[] = { + DECL_RFK_WC(0x12dc, 0x00000002), + DECL_RFK_WS(0x032c, 0x00010000), + DECL_RFK_WM(0x030c, 0x0f000000, 0x0000000c), + DECL_RFK_WS(0x032c, 0x40000000), + DECL_RFK_WC(0x12b8, 0x40000000), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_addck_restore_defs_a); + +static const struct rtw89_reg5_def rtw8852a_rfk_addck_reset_defs_b[] = { + DECL_RFK_WS(0x32b8, 0x40000000), + DECL_RFK_WC(0x032c, 0x40000000), + DECL_RFK_WC(0x032c, 0x00400000), + DECL_RFK_WS(0x032c, 0x00400000), + DECL_RFK_WS(0x030c, 0x0f000000), + DECL_RFK_WC(0x032c, 0x00010000), + DECL_RFK_WS(0x32dc, 0x00000002), + DECL_RFK_WM(0x030c, 0x0f000000, 0x00000003), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_addck_reset_defs_b); + +static const struct rtw89_reg5_def rtw8852a_rfk_addck_trigger_defs_b[] = { + DECL_RFK_WS(0x32d8, 0x000000c0), + DECL_RFK_WS(0x32d8, 0x00000800), + DECL_RFK_WC(0x32d8, 0x00000800), + DECL_RFK_DELAY(1), + DECL_RFK_WM(0x32d8, 0x00000300, 0x00000001), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_addck_trigger_defs_b); + +static const struct rtw89_reg5_def rtw8852a_rfk_addck_restore_defs_b[] = { + DECL_RFK_WC(0x32dc, 0x00000002), + DECL_RFK_WS(0x032c, 0x00010000), + DECL_RFK_WM(0x030c, 0x0f000000, 0x0000000c), + DECL_RFK_WS(0x032c, 0x40000000), + DECL_RFK_WC(0x32b8, 0x40000000), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_addck_restore_defs_b); + +static const struct rtw89_reg5_def rtw8852a_rfk_check_dadc_defs_f_a[] = { + DECL_RFK_WC(0x032c, 0x40000000), + DECL_RFK_WS(0x030c, 0x0f000000), + DECL_RFK_WM(0x030c, 0x0f000000, 0x00000003), + DECL_RFK_WC(0x032c, 0x00010000), + DECL_RFK_WS(0x12dc, 0x00000001), + DECL_RFK_WS(0x12e8, 0x00000004), + DECL_RFK_WRF(0x0, 0x8f, 0x02000, 0x00001), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_check_dadc_defs_f_a); + +static const struct rtw89_reg5_def rtw8852a_rfk_check_dadc_defs_f_b[] = { + DECL_RFK_WC(0x032c, 0x40000000), + DECL_RFK_WS(0x030c, 0x0f000000), + DECL_RFK_WM(0x030c, 0x0f000000, 0x00000003), + DECL_RFK_WC(0x032c, 0x00010000), + DECL_RFK_WS(0x32dc, 0x00000001), + DECL_RFK_WS(0x32e8, 0x00000004), + DECL_RFK_WRF(0x1, 0x8f, 0x02000, 0x00001), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_check_dadc_defs_f_b); + +static const struct rtw89_reg5_def rtw8852a_rfk_check_dadc_defs_r_a[] = { + DECL_RFK_WC(0x12dc, 0x00000001), + DECL_RFK_WC(0x12e8, 0x00000004), + DECL_RFK_WRF(0x0, 0x8f, 0x02000, 0x00000), + DECL_RFK_WM(0x032c, 0x00010000, 0x00000001), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_check_dadc_defs_r_a); + +static const struct rtw89_reg5_def rtw8852a_rfk_check_dadc_defs_r_b[] = { + DECL_RFK_WC(0x32dc, 0x00000001), + DECL_RFK_WC(0x32e8, 0x00000004), + DECL_RFK_WRF(0x1, 0x8f, 0x02000, 0x00000), + DECL_RFK_WM(0x032c, 0x00010000, 0x00000001), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_check_dadc_defs_r_b); + +static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_f_a[] = { + DECL_RFK_WS(0x5e00, 0x00000008), + DECL_RFK_WC(0x5e10, 0x80000000), + DECL_RFK_WS(0x5e50, 0x00000008), + DECL_RFK_WC(0x5e60, 0x80000000), + DECL_RFK_WS(0x12a0, 0x00008000), + DECL_RFK_WM(0x12a0, 0x00007000, 0x00000003), + DECL_RFK_WS(0x12b8, 0x40000000), + DECL_RFK_WS(0x030c, 0x10000000), + DECL_RFK_WC(0x032c, 0x80000000), + DECL_RFK_WS(0x12e0, 0x00010000), + DECL_RFK_WS(0x12e4, 0x0c000000), + DECL_RFK_WM(0x5e00, 0x03ff0000, 0x00000030), + DECL_RFK_WM(0x5e50, 0x03ff0000, 0x00000030), + DECL_RFK_WC(0x5e00, 0x0c000000), + DECL_RFK_WC(0x5e50, 0x0c000000), + DECL_RFK_WC(0x5e0c, 0x00000008), + DECL_RFK_WC(0x5e5c, 0x00000008), + DECL_RFK_WS(0x5e0c, 0x00000001), + DECL_RFK_WS(0x5e5c, 0x00000001), + DECL_RFK_DELAY(1), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_f_a); + +static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_m_a[] = { + DECL_RFK_WC(0x12e4, 0x0c000000), + DECL_RFK_WS(0x5e0c, 0x00000008), + DECL_RFK_WS(0x5e5c, 0x00000008), + DECL_RFK_DELAY(1), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_m_a); + +static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_r_a[] = { + DECL_RFK_WC(0x5e0c, 0x00000001), + DECL_RFK_WC(0x5e5c, 0x00000001), + DECL_RFK_WC(0x12e0, 0x00010000), + DECL_RFK_WC(0x12a0, 0x00008000), + DECL_RFK_WS(0x12a0, 0x00007000), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_r_a); + +static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_f_b[] = { + DECL_RFK_WS(0x7e00, 0x00000008), + DECL_RFK_WC(0x7e10, 0x80000000), + DECL_RFK_WS(0x7e50, 0x00000008), + DECL_RFK_WC(0x7e60, 0x80000000), + DECL_RFK_WS(0x32a0, 0x00008000), + DECL_RFK_WM(0x32a0, 0x00007000, 0x00000003), + DECL_RFK_WS(0x32b8, 0x40000000), + DECL_RFK_WS(0x030c, 0x10000000), + DECL_RFK_WC(0x032c, 0x80000000), + DECL_RFK_WS(0x32e0, 0x00010000), + DECL_RFK_WS(0x32e4, 0x0c000000), + DECL_RFK_WM(0x7e00, 0x03ff0000, 0x00000030), + DECL_RFK_WM(0x7e50, 0x03ff0000, 0x00000030), + DECL_RFK_WC(0x7e00, 0x0c000000), + DECL_RFK_WC(0x7e50, 0x0c000000), + DECL_RFK_WC(0x7e0c, 0x00000008), + DECL_RFK_WC(0x7e5c, 0x00000008), + DECL_RFK_WS(0x7e0c, 0x00000001), + DECL_RFK_WS(0x7e5c, 0x00000001), + DECL_RFK_DELAY(1), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_f_b); + +static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_m_b[] = { + DECL_RFK_WC(0x32e4, 0x0c000000), + DECL_RFK_WM(0x7e0c, 0x00000008, 0x00000001), + DECL_RFK_WM(0x7e5c, 0x00000008, 0x00000001), + DECL_RFK_DELAY(1), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_m_b); + +static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_r_b[] = { + DECL_RFK_WC(0x7e0c, 0x00000001), + DECL_RFK_WC(0x7e5c, 0x00000001), + DECL_RFK_WC(0x32e0, 0x00010000), + DECL_RFK_WC(0x32a0, 0x00008000), + DECL_RFK_WS(0x32a0, 0x00007000), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_r_b); + +static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_sf_defs_a[] = { + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000101), + DECL_RFK_WS(0x12b8, 0x40000000), + DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), + DECL_RFK_WM(0x032c, 0xffff0000, 0x00000041), + DECL_RFK_WS(0x12b8, 0x10000000), + DECL_RFK_WS(0x58c8, 0x01000000), + DECL_RFK_WS(0x5864, 0xc0000000), + DECL_RFK_WS(0x2008, 0x01ffffff), + DECL_RFK_WS(0x0c1c, 0x00000004), + DECL_RFK_WS(0x0700, 0x08000000), + DECL_RFK_WS(0x0c70, 0x000003ff), + DECL_RFK_WS(0x0c60, 0x00000003), + DECL_RFK_WS(0x0c6c, 0x00000001), + DECL_RFK_WS(0x58ac, 0x08000000), + DECL_RFK_WS(0x0c3c, 0x00000200), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_sf_defs_a); + +static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_sr_defs_a[] = { + DECL_RFK_WS(0x4490, 0x80000000), + DECL_RFK_WS(0x12a0, 0x00007000), + DECL_RFK_WS(0x12a0, 0x00008000), + DECL_RFK_WM(0x12a0, 0x00070000, 0x00000003), + DECL_RFK_WS(0x12a0, 0x00080000), + DECL_RFK_WS(0x0700, 0x01000000), + DECL_RFK_WM(0x0700, 0x06000000, 0x00000002), + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00001111), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_sr_defs_a); + +static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_sf_defs_b[] = { + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000202), + DECL_RFK_WS(0x32b8, 0x40000000), + DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), + DECL_RFK_WM(0x032c, 0xffff0000, 0x00000041), + DECL_RFK_WS(0x32b8, 0x10000000), + DECL_RFK_WS(0x78c8, 0x01000000), + DECL_RFK_WS(0x7864, 0xc0000000), + DECL_RFK_WS(0x2008, 0x01ffffff), + DECL_RFK_WS(0x2c1c, 0x00000004), + DECL_RFK_WS(0x2700, 0x08000000), + DECL_RFK_WS(0x0c70, 0x000003ff), + DECL_RFK_WS(0x0c60, 0x00000003), + DECL_RFK_WS(0x0c6c, 0x00000001), + DECL_RFK_WS(0x78ac, 0x08000000), + DECL_RFK_WS(0x2c3c, 0x00000200), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_sf_defs_b); + +static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_sr_defs_b[] = { + DECL_RFK_WS(0x6490, 0x80000000), + DECL_RFK_WS(0x32a0, 0x00007000), + DECL_RFK_WS(0x32a0, 0x00008000), + DECL_RFK_WM(0x32a0, 0x00070000, 0x00000003), + DECL_RFK_WS(0x32a0, 0x00080000), + DECL_RFK_WS(0x2700, 0x01000000), + DECL_RFK_WM(0x2700, 0x06000000, 0x00000002), + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00002222), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_sr_defs_b); + +static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_s_defs_ab[] = { + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000303), + DECL_RFK_WS(0x12b8, 0x40000000), + DECL_RFK_WS(0x32b8, 0x40000000), + DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), + DECL_RFK_WM(0x032c, 0xffff0000, 0x00000041), + DECL_RFK_WS(0x12b8, 0x10000000), + DECL_RFK_WS(0x58c8, 0x01000000), + DECL_RFK_WS(0x78c8, 0x01000000), + DECL_RFK_WS(0x5864, 0xc0000000), + DECL_RFK_WS(0x7864, 0xc0000000), + DECL_RFK_WS(0x2008, 0x01ffffff), + DECL_RFK_WS(0x0c1c, 0x00000004), + DECL_RFK_WS(0x0700, 0x08000000), + DECL_RFK_WS(0x0c70, 0x000003ff), + DECL_RFK_WS(0x0c60, 0x00000003), + DECL_RFK_WS(0x0c6c, 0x00000001), + DECL_RFK_WS(0x58ac, 0x08000000), + DECL_RFK_WS(0x78ac, 0x08000000), + DECL_RFK_WS(0x0c3c, 0x00000200), + DECL_RFK_WS(0x2344, 0x80000000), + DECL_RFK_WS(0x4490, 0x80000000), + DECL_RFK_WS(0x12a0, 0x00007000), + DECL_RFK_WS(0x12a0, 0x00008000), + DECL_RFK_WM(0x12a0, 0x00070000, 0x00000003), + DECL_RFK_WS(0x12a0, 0x00080000), + DECL_RFK_WM(0x32a0, 0x00070000, 0x00000003), + DECL_RFK_WS(0x32a0, 0x00080000), + DECL_RFK_WS(0x0700, 0x01000000), + DECL_RFK_WM(0x0700, 0x06000000, 0x00000002), + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00003333), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_s_defs_ab); + +static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_r_defs_a[] = { + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000101), + DECL_RFK_WC(0x12b8, 0x40000000), + DECL_RFK_WC(0x5864, 0xc0000000), + DECL_RFK_WC(0x2008, 0x01ffffff), + DECL_RFK_WC(0x0c1c, 0x00000004), + DECL_RFK_WC(0x0700, 0x08000000), + DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), + DECL_RFK_WM(0x0c70, 0x000003e0, 0x00000003), + DECL_RFK_WC(0x12a0, 0x000ff000), + DECL_RFK_WC(0x0700, 0x07000000), + DECL_RFK_WC(0x5864, 0x20000000), + DECL_RFK_WC(0x0c3c, 0x00000200), + DECL_RFK_WC(0x2344, 0x80000000), + DECL_RFK_WC(0x20fc, 0xffff0000), + DECL_RFK_WC(0x58c8, 0x01000000), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_r_defs_a); + +static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_r_defs_b[] = { + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000202), + DECL_RFK_WC(0x32b8, 0x40000000), + DECL_RFK_WC(0x7864, 0xc0000000), + DECL_RFK_WC(0x2008, 0x01ffffff), + DECL_RFK_WC(0x2c1c, 0x00000004), + DECL_RFK_WC(0x2700, 0x08000000), + DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), + DECL_RFK_WM(0x0c70, 0x000003e0, 0x00000003), + DECL_RFK_WC(0x32a0, 0x000ff000), + DECL_RFK_WC(0x2700, 0x07000000), + DECL_RFK_WC(0x7864, 0x20000000), + DECL_RFK_WC(0x2c3c, 0x00000200), + DECL_RFK_WC(0x2344, 0x80000000), + DECL_RFK_WC(0x20fc, 0xffff0000), + DECL_RFK_WC(0x78c8, 0x01000000), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_r_defs_b); + +static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_r_defs_ab[] = { + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000303), + DECL_RFK_WC(0x12b8, 0x40000000), + DECL_RFK_WC(0x32b8, 0x40000000), + DECL_RFK_WC(0x5864, 0xc0000000), + DECL_RFK_WC(0x7864, 0xc0000000), + DECL_RFK_WC(0x2008, 0x01ffffff), + DECL_RFK_WC(0x0c1c, 0x00000004), + DECL_RFK_WC(0x0700, 0x08000000), + DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), + DECL_RFK_WM(0x0c70, 0x000003e0, 0x00000003), + DECL_RFK_WC(0x12a0, 0x000ff000), + DECL_RFK_WC(0x32a0, 0x000ff000), + DECL_RFK_WC(0x0700, 0x07000000), + DECL_RFK_WC(0x5864, 0x20000000), + DECL_RFK_WC(0x7864, 0x20000000), + DECL_RFK_WC(0x0c3c, 0x00000200), + DECL_RFK_WC(0x2344, 0x80000000), + DECL_RFK_WC(0x20fc, 0xffff0000), + DECL_RFK_WC(0x58c8, 0x01000000), + DECL_RFK_WC(0x78c8, 0x01000000), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_r_defs_ab); + +static const struct rtw89_reg5_def rtw8852a_rfk_dpk_lbk_rxiqk_defs_f[] = { + DECL_RFK_WM(0x030c, 0xff000000, 0x0000000f), + DECL_RFK_DELAY(1), + DECL_RFK_WM(0x030c, 0xff000000, 0x00000003), + DECL_RFK_WM(0x032c, 0xffff0000, 0x0000a001), + DECL_RFK_DELAY(1), + DECL_RFK_WM(0x032c, 0xffff0000, 0x0000a041), + DECL_RFK_WS(0x8074, 0x80000000), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dpk_lbk_rxiqk_defs_f); + +static const struct rtw89_reg5_def rtw8852a_rfk_dpk_lbk_rxiqk_defs_r[] = { + DECL_RFK_WC(0x8074, 0x80000000), + DECL_RFK_WM(0x030c, 0xff000000, 0x0000001f), + DECL_RFK_DELAY(1), + DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), + DECL_RFK_WM(0x032c, 0xffff0000, 0x00000001), + DECL_RFK_DELAY(1), + DECL_RFK_WM(0x032c, 0xffff0000, 0x00000041), + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000303), + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00003333), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dpk_lbk_rxiqk_defs_r); + +static const struct rtw89_reg5_def rtw8852a_rfk_dpk_pas_read_defs[] = { + DECL_RFK_WM(0x80d4, 0x00ff0000, 0x00000006), + DECL_RFK_WC(0x80bc, 0x00004000), + DECL_RFK_WM(0x80c0, 0x00ff0000, 0x00000008), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_dpk_pas_read_defs); + +static const struct rtw89_reg5_def rtw8852a_rfk_iqk_set_defs_nondbcc_path01[] = { + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000303), + DECL_RFK_WM(0x5864, 0x18000000, 0x00000003), + DECL_RFK_WM(0x7864, 0x18000000, 0x00000003), + DECL_RFK_WM(0x12b8, 0x40000000, 0x00000001), + DECL_RFK_WM(0x32b8, 0x40000000, 0x00000001), + DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), + DECL_RFK_WM(0x032c, 0xffff0000, 0x00000001), + DECL_RFK_WM(0x12b8, 0x10000000, 0x00000001), + DECL_RFK_WM(0x58c8, 0x01000000, 0x00000001), + DECL_RFK_WM(0x78c8, 0x01000000, 0x00000001), + DECL_RFK_WM(0x5864, 0xc0000000, 0x00000003), + DECL_RFK_WM(0x7864, 0xc0000000, 0x00000003), + DECL_RFK_WM(0x2008, 0x01ffffff, 0x01ffffff), + DECL_RFK_WM(0x0c1c, 0x00000004, 0x00000001), + DECL_RFK_WM(0x0700, 0x08000000, 0x00000001), + DECL_RFK_WM(0x0c70, 0x000003ff, 0x000003ff), + DECL_RFK_WM(0x0c60, 0x00000003, 0x00000003), + DECL_RFK_WM(0x0c6c, 0x00000001, 0x00000001), + DECL_RFK_WM(0x58ac, 0x08000000, 0x00000001), + DECL_RFK_WM(0x78ac, 0x08000000, 0x00000001), + DECL_RFK_WM(0x0c3c, 0x00000200, 0x00000001), + DECL_RFK_WM(0x2320, 0x00000001, 0x00000001), + DECL_RFK_WM(0x4490, 0x80000000, 0x00000001), + DECL_RFK_WM(0x12a0, 0x00007000, 0x00000007), + DECL_RFK_WM(0x12a0, 0x00008000, 0x00000001), + DECL_RFK_WM(0x12a0, 0x00070000, 0x00000003), + DECL_RFK_WM(0x12a0, 0x00080000, 0x00000001), + DECL_RFK_WM(0x32a0, 0x00070000, 0x00000003), + DECL_RFK_WM(0x32a0, 0x00080000, 0x00000001), + DECL_RFK_WM(0x0700, 0x01000000, 0x00000001), + DECL_RFK_WM(0x0700, 0x06000000, 0x00000002), + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00003333), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_iqk_set_defs_nondbcc_path01); + +static const struct rtw89_reg5_def rtw8852a_rfk_iqk_set_defs_dbcc_path0[] = { + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000101), + DECL_RFK_WM(0x5864, 0x18000000, 0x00000003), + DECL_RFK_WM(0x7864, 0x18000000, 0x00000003), + DECL_RFK_WM(0x12b8, 0x40000000, 0x00000001), + DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), + DECL_RFK_WM(0x032c, 0xffff0000, 0x00000001), + DECL_RFK_WM(0x12b8, 0x10000000, 0x00000001), + DECL_RFK_WM(0x58c8, 0x01000000, 0x00000001), + DECL_RFK_WM(0x5864, 0xc0000000, 0x00000003), + DECL_RFK_WM(0x2008, 0x01ffffff, 0x01ffffff), + DECL_RFK_WM(0x0c1c, 0x00000004, 0x00000001), + DECL_RFK_WM(0x0700, 0x08000000, 0x00000001), + DECL_RFK_WM(0x0c70, 0x000003ff, 0x000003ff), + DECL_RFK_WM(0x0c60, 0x00000003, 0x00000003), + DECL_RFK_WM(0x0c6c, 0x00000001, 0x00000001), + DECL_RFK_WM(0x58ac, 0x08000000, 0x00000001), + DECL_RFK_WM(0x0c3c, 0x00000200, 0x00000001), + DECL_RFK_WM(0x2320, 0x00000001, 0x00000001), + DECL_RFK_WM(0x4490, 0x80000000, 0x00000001), + DECL_RFK_WM(0x12a0, 0x00007000, 0x00000007), + DECL_RFK_WM(0x12a0, 0x00008000, 0x00000001), + DECL_RFK_WM(0x12a0, 0x00070000, 0x00000003), + DECL_RFK_WM(0x12a0, 0x00080000, 0x00000001), + DECL_RFK_WM(0x0700, 0x01000000, 0x00000001), + DECL_RFK_WM(0x0700, 0x06000000, 0x00000002), + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00001111), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_iqk_set_defs_dbcc_path0); + +static const struct rtw89_reg5_def rtw8852a_rfk_iqk_set_defs_dbcc_path1[] = { + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000202), + DECL_RFK_WM(0x7864, 0x18000000, 0x00000003), + DECL_RFK_WM(0x32b8, 0x40000000, 0x00000001), + DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), + DECL_RFK_WM(0x032c, 0xffff0000, 0x00000001), + DECL_RFK_WM(0x32b8, 0x10000000, 0x00000001), + DECL_RFK_WM(0x78c8, 0x01000000, 0x00000001), + DECL_RFK_WM(0x7864, 0xc0000000, 0x00000003), + DECL_RFK_WM(0x2008, 0x01ffffff, 0x01ffffff), + DECL_RFK_WM(0x2c1c, 0x00000004, 0x00000001), + DECL_RFK_WM(0x2700, 0x08000000, 0x00000001), + DECL_RFK_WM(0x0c70, 0x000003ff, 0x000003ff), + DECL_RFK_WM(0x0c60, 0x00000003, 0x00000003), + DECL_RFK_WM(0x0c6c, 0x00000001, 0x00000001), + DECL_RFK_WM(0x78ac, 0x08000000, 0x00000001), + DECL_RFK_WM(0x2c3c, 0x00000200, 0x00000001), + DECL_RFK_WM(0x6490, 0x80000000, 0x00000001), + DECL_RFK_WM(0x32a0, 0x00007000, 0x00000007), + DECL_RFK_WM(0x32a0, 0x00008000, 0x00000001), + DECL_RFK_WM(0x32a0, 0x00070000, 0x00000003), + DECL_RFK_WM(0x32a0, 0x00080000, 0x00000001), + DECL_RFK_WM(0x2700, 0x01000000, 0x00000001), + DECL_RFK_WM(0x2700, 0x06000000, 0x00000002), + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00002222), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_iqk_set_defs_dbcc_path1); + +static const struct rtw89_reg5_def rtw8852a_rfk_iqk_restore_defs_nondbcc_path01[] = { + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000303), + DECL_RFK_WM(0x12b8, 0x40000000, 0x00000000), + DECL_RFK_WM(0x32b8, 0x40000000, 0x00000000), + DECL_RFK_WM(0x5864, 0xc0000000, 0x00000000), + DECL_RFK_WM(0x7864, 0xc0000000, 0x00000000), + DECL_RFK_WM(0x2008, 0x01ffffff, 0x00000000), + DECL_RFK_WM(0x0c1c, 0x00000004, 0x00000000), + DECL_RFK_WM(0x0700, 0x08000000, 0x00000000), + DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), + DECL_RFK_WM(0x0c70, 0x000003e0, 0x00000003), + DECL_RFK_WM(0x12a0, 0x000ff000, 0x00000000), + DECL_RFK_WM(0x32a0, 0x000ff000, 0x00000000), + DECL_RFK_WM(0x0700, 0x07000000, 0x00000000), + DECL_RFK_WM(0x5864, 0x20000000, 0x00000000), + DECL_RFK_WM(0x7864, 0x20000000, 0x00000000), + DECL_RFK_WM(0x0c3c, 0x00000200, 0x00000000), + DECL_RFK_WM(0x2320, 0x00000001, 0x00000000), + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000000), + DECL_RFK_WM(0x58c8, 0x01000000, 0x00000000), + DECL_RFK_WM(0x78c8, 0x01000000, 0x00000000), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_iqk_restore_defs_nondbcc_path01); + +static const struct rtw89_reg5_def rtw8852a_rfk_iqk_restore_defs_dbcc_path0[] = { + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000101), + DECL_RFK_WM(0x12b8, 0x40000000, 0x00000000), + DECL_RFK_WM(0x5864, 0xc0000000, 0x00000000), + DECL_RFK_WM(0x2008, 0x01ffffff, 0x00000000), + DECL_RFK_WM(0x0c1c, 0x00000004, 0x00000000), + DECL_RFK_WM(0x0700, 0x08000000, 0x00000000), + DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), + DECL_RFK_WM(0x0c70, 0x000003e0, 0x00000003), + DECL_RFK_WM(0x12a0, 0x000ff000, 0x00000000), + DECL_RFK_WM(0x0700, 0x07000000, 0x00000000), + DECL_RFK_WM(0x5864, 0x20000000, 0x00000000), + DECL_RFK_WM(0x0c3c, 0x00000200, 0x00000000), + DECL_RFK_WM(0x2320, 0x00000001, 0x00000000), + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000000), + DECL_RFK_WM(0x58c8, 0x01000000, 0x00000000), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_iqk_restore_defs_dbcc_path0); + +static const struct rtw89_reg5_def rtw8852a_rfk_iqk_restore_defs_dbcc_path1[] = { + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000202), + DECL_RFK_WM(0x32b8, 0x40000000, 0x00000000), + DECL_RFK_WM(0x7864, 0xc0000000, 0x00000000), + DECL_RFK_WM(0x2008, 0x01ffffff, 0x00000000), + DECL_RFK_WM(0x2c1c, 0x00000004, 0x00000000), + DECL_RFK_WM(0x2700, 0x08000000, 0x00000000), + DECL_RFK_WM(0x0cf0, 0x000001ff, 0x00000000), + DECL_RFK_WM(0x32a0, 0x000ff000, 0x00000000), + DECL_RFK_WM(0x2700, 0x07000000, 0x00000000), + DECL_RFK_WM(0x7864, 0x20000000, 0x00000000), + DECL_RFK_WM(0x2c3c, 0x00000200, 0x00000000), + DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000000), + DECL_RFK_WM(0x78c8, 0x01000000, 0x00000000), + DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), +}; + +DECLARE_RFK_TBL(rtw8852a_rfk_iqk_restore_defs_dbcc_path1); diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.h b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.h new file mode 100644 index 000000000000..2ec62f9b8a56 --- /dev/null +++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* Copyright(c) 2019-2020 Realtek Corporation + */ + +#ifndef __RTW89_8852A_RFK_TABLE_H__ +#define __RTW89_8852A_RFK_TABLE_H__ + +#include "core.h" + +enum rtw89_rfk_flag { + RTW89_RFK_F_WRF = 0, + RTW89_RFK_F_WM = 1, + RTW89_RFK_F_WS = 2, + RTW89_RFK_F_WC = 3, + RTW89_RFK_F_DELAY = 4, + RTW89_RFK_F_NUM, +}; + +struct rtw89_rfk_tbl { + const struct rtw89_reg5_def *defs; + u32 size; +}; + +#define DECLARE_RFK_TBL(_name) \ +const struct rtw89_rfk_tbl _name ## _tbl = { \ + .defs = _name, \ + .size = ARRAY_SIZE(_name), \ +} + +#define DECL_RFK_WRF(_path, _addr, _mask, _data) \ + {.flag = RTW89_RFK_F_WRF, \ + .path = _path, \ + .addr = _addr, \ + .mask = _mask, \ + .data = _data,} + +#define DECL_RFK_WM(_addr, _mask, _data) \ + {.flag = RTW89_RFK_F_WM, \ + .addr = _addr, \ + .mask = _mask, \ + .data = _data,} + +#define DECL_RFK_WS(_addr, _mask) \ + {.flag = RTW89_RFK_F_WS, \ + .addr = _addr, \ + .mask = _mask,} + +#define DECL_RFK_WC(_addr, _mask) \ + {.flag = RTW89_RFK_F_WC, \ + .addr = _addr, \ + .mask = _mask,} + +#define DECL_RFK_DELAY(_data) \ + {.flag = RTW89_RFK_F_DELAY, \ + .data = _data,} + +extern const struct rtw89_rfk_tbl rtw8852a_tssi_sys_defs_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_sys_defs_2g_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_sys_defs_5g_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_txpwr_ctrl_bb_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_txpwr_ctrl_bb_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_dck_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_dck_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_dac_gain_tbl_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_dac_gain_tbl_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_slope_cal_org_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_slope_cal_org_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_rf_gap_tbl_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_rf_gap_tbl_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_slope_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_slope_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_track_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_track_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_txagc_ofst_mv_avg_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_txagc_ofst_mv_avg_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_a_2g_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_a_5g_1_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_a_5g_3_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_a_5g_4_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_b_2g_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_b_5g_1_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_b_5g_3_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_b_5g_4_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_enable_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_enable_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_tssi_disable_defs_tbl; + +extern const struct rtw89_rfk_tbl rtw8852a_rfk_afe_init_defs_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_reload_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_reload_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_addc_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_addc_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_reset_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_trigger_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_restore_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_reset_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_trigger_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_restore_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_dadc_defs_f_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_dadc_defs_f_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_dadc_defs_r_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_dadc_defs_r_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_f_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_m_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_r_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_f_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_m_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_r_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_sf_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_sr_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_sf_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_sr_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_s_defs_ab_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_r_defs_a_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_r_defs_b_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_r_defs_ab_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_lbk_rxiqk_defs_f_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_lbk_rxiqk_defs_r_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_pas_read_defs_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_set_defs_nondbcc_path01_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_set_defs_dbcc_path0_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_set_defs_dbcc_path1_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_restore_defs_nondbcc_path01_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_restore_defs_dbcc_path0_tbl; +extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_restore_defs_dbcc_path1_tbl; + +#endif

[V2,15/18] rtw89: 8852a: add 8852a RFK tables

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