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+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/* Copyright(c) 2019-2022, Celeno Communications Ltd. */
+
+#ifndef CL_HW_H
+#define CL_HW_H
+
+#include <linux/module.h>
+
+#include "traffic.h"
+#include "temperature.h"
+#include "dfs.h"
+#include "calib.h"
+#include "ipc_shared.h"
+#include "fw.h"
+#include "rates.h"
+#include "def.h"
+#include "tx.h"
+#include "radio.h"
+#include "mac80211.h"
+#include "scan.h"
+#include "rx.h"
+#include "wrs.h"
+#include "vns.h"
+#include "sta.h"
+#include "debug.h"
+#include "chip.h"
+#include "recovery.h"
+#include "bf.h"
+#include "power.h"
+#include "phy.h"
+#include "vif.h"
+#include "tcv.h"
+#include "sounding.h"
+#include "version.h"
+
+#define cl_hw_get_iface_conf(cl_hw) atomic_read(&(cl_hw)->iface_conf)
+#define cl_hw_set_iface_conf(cl_hw, value) atomic_set(&(cl_hw)->iface_conf, value)
+
+/* Structure used to store information regarding E2A msg buffers in the driver */
+struct cl_e2a_msg_elem {
+ struct cl_ipc_e2a_msg *msgbuf_ptr;
+ dma_addr_t dma_addr;
+};
+
+enum cl_iface_conf {
+ CL_IFCONF_AP,
+ CL_IFCONF_STA,
+ CL_IFCONF_REPEATER,
+ CL_IFCONF_MESH_AP,
+ CL_IFCONF_MESH_ONLY,
+
+ CL_IFCONF_MAX
+};
+
+struct cl_hw_asserts_info {
+ /* Timestamp (jiffies) of the last CL_MIN_ASSERT_CNT hw assert. */
+ unsigned long timestamp[CL_MIN_ASSERT_CNT];
+ /* Hw assert index. */
+ u8 index;
+ /* Indicate if hw_restart was schedule */
+ u8 restart_sched;
+};
+
+struct cl_hw {
+ u8 idx; /* Global index (0-3) */
+ u8 tcv_idx; /* Transceiver index (0-1) */
+ u8 sx_idx;
+ struct cl_tcv_conf *conf;
+ struct cl_chip *chip;
+ struct ieee80211_hw *hw;
+ const struct cl_driver_ops *drv_ops;
+ struct cl_vif_db vif_db;
+ atomic_t iface_conf;
+ u32 num_ap_started;
+ u8 hw_mode;
+ enum cl_wireless_mode wireless_mode;
+ u8 tx_power_version;
+ struct cl_vif *mc_vif;
+ u8 bw;
+ u32 channel;
+ u32 primary_freq;
+ u32 center_freq;
+ enum nl80211_band nl_band;
+ u8 num_antennas;
+ u8 mask_num_antennas;
+ u8 first_ant;
+ u8 first_riu_chain;
+ u8 last_riu_chain;
+ u8 max_antennas;
+ struct cl_tx_db tx_db;
+ struct cl_sta_db cl_sta_db;
+ struct cl_ipc_e2a_irq ipc_e2a_irq;
+ struct cl_controller_reg controller_reg;
+ struct ieee80211_supported_band sband;
+ void (*ipc_host2xmac_trigger_set)(struct cl_chip *chip, u32 value);
+ unsigned long drv_flags;
+ unsigned long tx_disable_flags;
+ struct cl_ipc_host_env *ipc_env;
+ spinlock_t tx_lock_agg;
+ spinlock_t tx_lock_cfm_agg;
+ spinlock_t tx_lock_single;
+ spinlock_t tx_lock_bcmc;
+ struct mutex msg_tx_mutex;
+ wait_queue_head_t wait_queue; /* Synchronize driver<-->firmware message exchanges */
+ unsigned long cfm_flags[MAX_CFM_FLAGS];
+ void *msg_cfm_params[MM_MAX + DBG_MAX]; /* Array of pointers per received msg CFM */
+ bool msg_background;
+ wait_queue_head_t fw_sync_wq;
+ wait_queue_head_t radio_wait_queue;
+ struct cl_rx_elem *rx_elems;
+ struct cl_e2a_msg_elem *e2a_msg_elems;
+ struct cl_dbg_elem *dbg_elems;
+ struct cl_radar_elem *radar_elems;
+ struct dma_pool *txdesc_pool;
+ struct dma_pool *dbg_pool;
+ struct dma_pool *e2a_msg_pool;
+ struct dma_pool *radar_pool;
+ struct cl_debug_info dbginfo;
+ struct cl_hw_asserts_info assert_info;
+ char fw_prefix; /* Single character for fw prefix - l/u/s */
+ u8 fw_dst_kern_id; /* Firmware destination (LMAC/SMAC) */
+ bool fw_active; /* Firmware is active */
+ bool fw_send_start; /* Did driver already send a start request message to firmware? */
+ struct cl_dbg_data dbg_data;
+ struct cl_tx_power_info tx_pow_info[MAX_EXT_CHANNELS][MAX_ANTENNAS];
+ spinlock_t channel_info_lock;
+ struct cl_channel_info channel_info;
+ struct cl_phy_data_info phy_data_info;
+ u32 mask_hi;
+ u32 mask_low;
+ struct timer_list maintenance_slow_timer;
+ struct timer_list maintenance_fast_timer;
+ struct tasklet_struct tx_task;
+ struct list_head list_sched_q_agg;
+ struct list_head list_sched_q_single;
+ struct cl_req_agg_db req_agg_db[IPC_MAX_BA_SESSIONS];
+ u8 req_agg_queues;
+ u8 used_agg_queues;
+ bool is_stop_context;
+ struct workqueue_struct *drv_workqueue;
+ struct cl_amsdu_rx_state amsdu_rx_state;
+ struct cl_tx_queues *tx_queues;
+ struct kmem_cache *sw_txhdr_cache;
+ struct kmem_cache *amsdu_txhdr_cache;
+ u32 radio_stats[CL_RADIO_ERRORS_MAX];
+ struct cl_rx_path_info rx_info;
+ struct cl_prot_mode prot_mode;
+ struct cl_agg_cfm_queue agg_cfm_queues[IPC_MAX_BA_SESSIONS];
+ struct cl_single_cfm_queue single_cfm_queues[MAX_SINGLE_QUEUES];
+ struct cl_single_cfm_queue bcmc_cfm_queue;
+ atomic_t radio_lock;
+ struct cl_assoc_queue assoc_queue;
+ struct cl_wrs_db wrs_db;
+ struct cl_traffic_main traffic_db;
+ struct cl_power_db power_db;
+ struct cl_bf_db bf_db;
+ struct cl_edca_db edca_db;
+ struct cl_vns_db *vns_db;
+ struct cl_str_offload_env str_offload_env;
+ struct cl_dma_accessed fw_remote_rom;
+ struct cl_recovery_db recovery_db;
+ struct cl_radar_queue radar_queue;
+ struct tasklet_struct radar_tasklet;
+ struct cl_cached_fw cached_fw;
+ s8 rx_sensitivity[MAX_ANTENNAS];
+ struct cl_cca_db cca_db;
+ struct cl_noise_db noise_db;
+ struct cl_temp_comp_db temp_comp_db;
+ struct cl_sounding_db sounding;
+#ifdef CONFIG_CL8K_DYN_MCAST_RATE
+ struct cl_dyn_mcast_rate dyn_mcast_rate;
+#endif /* CONFIG_CL8K_DYN_MCAST_RATE */
+#ifdef CONFIG_CL8K_DYN_BCAST_RATE
+ struct cl_dyn_bcast_rate dyn_bcast_rate;
+#endif /* CONFIG_CL8K_DYN_BCAST_RATE */
+ struct cl_dfs_db dfs_db;
+ struct cl_version_db version_db;
+ bool entry_fixed_rate;
+ unsigned long last_tbtt_irq;
+ u16 smallest_beacon_int;
+ u32 tbtt_cnt;
+ u8 mesh_tbtt_div;
+ struct tasklet_struct tx_mesh_bcn_task;
+ u32 fw_recovery_cntr;
+ u32 rx_filter;
+ ptrdiff_t mac_hw_regs_offset;
+ ptrdiff_t phy_regs_offset;
+ struct list_head head_amsdu_txhdr_pool;
+ struct list_head head_sw_txhdr_pool;
+ spinlock_t lock_sw_txhdr_pool;
+ struct sk_buff_head rx_remote_queue_mac;
+ struct sk_buff_head rx_skb_queue;
+ struct tasklet_struct rx_tasklet;
+ struct tasklet_struct rx_resched_tasklet;
+ u8 fem_mode;
+ struct cl_tx_packet_cntr tx_packet_cntr;
+ struct cl_cpu_cntr cpu_cntr;
+ struct cl_iq_dcoc_data_info iq_dcoc_data_info;
+ struct cl_power_table_info power_table_info;
+ struct ieee80211_sband_iftype_data iftype_data[3];
+ bool motion_sense_dbg;
+ struct cl_power_truncate pwr_trunc;
+ struct mutex set_channel_mutex;
+ u8 radio_status;
+ u8 rf_crystal_mhz;
+ bool iq_cal_ready;
+ s8 rssi_simulate;
+ struct mac_address addresses[MAX_BSS_NUM];
+ struct cl_rx_stats *rx_stats; /* RX statistics for production mode. */
+ spinlock_t lock_stats;
+ u16 n_addresses;
+ u8 txamsdu_en;
+ bool reg_dbg;
+ s32 new_tx_power;
+ struct cl_rx_trigger_based_stats *tb_stats;
+ struct cl_rx_trigger_based_sta_stats *tb_sta_stats;
+ bool idle_async_set;
+ bool msg_calib_timeout;
+ struct cl_calib_work *calib_work;
+ struct cl_chan_scanner *scanner;
+ bool calib_runtime_needed;
+ u8 ht40_preffered_ch_type;
+ u8 sw_scan_in_progress;
+};
+
+void cl_hw_init(struct cl_chip *chip, struct cl_hw *cl_hw, u8 tcv_idx);
+void cl_hw_deinit(struct cl_hw *cl_hw, u8 tcv_idx);
+struct cl_hw *cl_hw_other_tcv(struct cl_hw *cl_hw);
+bool cl_hw_is_tcv0(struct cl_hw *cl_hw);
+bool cl_hw_is_tcv1(struct cl_hw *cl_hw);
+bool cl_hw_is_first_tcv(struct cl_hw *cl_hw);
+int cl_hw_set_antennas(struct cl_hw *cl_hw);
+u8 cl_hw_ant_shift(struct cl_hw *cl_hw);
+u8 cl_hw_ant_to_riu_chain(struct cl_hw *cl_hw, u8 ant);
+u8 cl_hw_ant_mask_to_riu_chain_mask(struct cl_hw *cl_hw, u8 ant_mask);
+bool cl_hw_is_prod_or_listener(struct cl_hw *cl_hw);
+void cl_hw_assert_info_init(struct cl_hw *cl_hw);
+void cl_hw_assert_print(struct cl_hw *cl_hw, struct cl_ipc_e2a_msg *msg);
+void cl_hw_assert_check(struct cl_hw *cl_hw);
+
+static inline void cl_sta_lock_bh(struct cl_hw *cl_hw)
+{
+ read_lock_bh(&cl_hw->cl_sta_db.lock);
+}
+
+static inline void cl_sta_unlock_bh(struct cl_hw *cl_hw)
+{
+ read_unlock_bh(&cl_hw->cl_sta_db.lock);
+}
+
+static inline void cl_sta_lock(struct cl_hw *cl_hw)
+{
+ read_lock(&cl_hw->cl_sta_db.lock);
+}
+
+static inline void cl_sta_unlock(struct cl_hw *cl_hw)
+{
+ read_unlock(&cl_hw->cl_sta_db.lock);
+}
+
+/* FW communication opses */
+static inline int cl_drv_ops_msg_fw_send(struct cl_hw *cl_hw,
+ const void *msg_params,
+ bool background)
+{
+ if (cl_hw->drv_ops->msg_fw_send)
+ return cl_hw->drv_ops->msg_fw_send(cl_hw, msg_params,
+ background);
+ return 0;
+}
+
+static inline void cl_drv_ops_pkt_fw_send(struct cl_hw *cl_hw,
+ struct cl_sw_txhdr *sw_txhdr,
+ struct cl_tx_queue *tx_queue)
+{
+ if (cl_hw->drv_ops->pkt_fw_send)
+ cl_hw->drv_ops->pkt_fw_send(cl_hw, sw_txhdr, tx_queue);
+}
+
+#endif /* CL_HW_H */