diff mbox series

[6/6] rtw89: 8852c: adjust mactxen delay of mac/phy interface

Message ID 20220704023453.19935-7-pkshih@realtek.com (mailing list archive)
State Accepted
Commit ee5469046474e2de82ef9992ce241224d944fe2b
Delegated to: Kalle Valo
Headers show
Series rtw89: correct settings of register and capability | expand

Commit Message

Ping-Ke Shih July 4, 2022, 2:34 a.m. UTC 
From: Chia-Yuan Li <leo.li@realtek.com>

mac_txen time is to inform TMAC tx after rx air end.
Modify 8852c value to meet TB SIFS time.

Signed-off-by: Chia-Yuan Li <leo.li@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
---
 drivers/net/wireless/realtek/rtw89/mac.c | 7 ++++++-
 drivers/net/wireless/realtek/rtw89/reg.h | 1 +
 2 files changed, 7 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c
index 799f000c59dcf..2c7185e07fd53 100644
--- a/drivers/net/wireless/realtek/rtw89/mac.c
+++ b/drivers/net/wireless/realtek/rtw89/mac.c
@@ -1754,7 +1754,12 @@  static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx)
 		return ret;
 
 	reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx);
-	rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, SIFS_MACTXEN_T1);
+	if (rtwdev->chip->chip_id == RTL8852C)
+		rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
+				   SIFS_MACTXEN_T1_V1);
+	else
+		rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
+				   SIFS_MACTXEN_T1);
 
 	if (rtwdev->chip->chip_id == RTL8852B) {
 		reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx);
diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h
index 986e27c445aa7..ef6f24d1801e5 100644
--- a/drivers/net/wireless/realtek/rtw89/reg.h
+++ b/drivers/net/wireless/realtek/rtw89/reg.h
@@ -1882,6 +1882,7 @@ 
 #define B_AX_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8)
 #define B_AX_SIFS_MACTXEN_T1_MASK GENMASK(6, 0)
 #define SIFS_MACTXEN_T1 0x47
+#define SIFS_MACTXEN_T1_V1 0x41
 
 #define R_AX_CCA_CFG_0 0xC340
 #define R_AX_CCA_CFG_0_C1 0xE340