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[5/5] wifi: rtw89: move software DCFO compensation setting to proper position

Message ID 20231016065115.751662-6-pkshih@realtek.com (mailing list archive)
State Accepted
Commit 388df37938da70d68a6c115c8800f62533c0afb5
Delegated to: Kalle Valo
Headers show
Series wifi: rtw89: add fields of PHY registers of BSS color and CFO for WiFi 7 chips | expand

Commit Message

Ping-Ke Shih Oct. 16, 2023, 6:51 a.m. UTC 
From: Cheng-Chieh Hsieh <cj.hsieh@realtek.com>

We need this register setting only for the software DCFO(digital carrier
frequency offset) compensation so we move it to the proper position to
prevent the incorrect setting.

Signed-off-by: Cheng-Chieh Hsieh <cj.hsieh@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
---
 drivers/net/wireless/realtek/rtw89/phy.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c
index 3b671a314e60..17ccc9efed28 100644
--- a/drivers/net/wireless/realtek/rtw89/phy.c
+++ b/drivers/net/wireless/realtek/rtw89/phy.c
@@ -2588,12 +2588,14 @@  static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev)
 	rtw89_phy_set_phy_regs(rtwdev, cfo->comp, cfo->weighting_mask, 8);
 
 	if (chip->chip_gen == RTW89_CHIP_AX) {
-		if (chip->cfo_hw_comp)
+		if (chip->cfo_hw_comp) {
 			rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2,
 					   B_AX_PWR_UL_CFO_MASK, 0x6);
-		else
+		} else {
+			rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1);
 			rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2,
 					  B_AX_PWR_UL_CFO_MASK);
+		}
 	}
 }
 
@@ -2617,7 +2619,6 @@  static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev)
 	rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n",
 		    cfo->crystal_cap_default);
 	rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true);
-	rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1);
 	rtw89_dcfo_comp_init(rtwdev);
 	cfo->cfo_timer_ms = 2000;
 	cfo->cfo_trig_by_timer_en = false;