diff mbox

[RFC,6/7] ath9k_hw: Program correct PLL value for AR9565

Message ID 20554.62374.945320.866841@gargle.gargle.HOWL (mailing list archive)
State Not Applicable, archived
Headers show

Commit Message

Sujith Manoharan Sept. 8, 2012, 7:28 a.m. UTC 
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
---
 drivers/net/wireless/ath/ath9k/hw.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

Comments

Felix Fietkau Sept. 8, 2012, 8:08 a.m. UTC | #1 
On 2012-09-08 9:28 AM, Sujith Manoharan wrote:
> Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
> ---
>  drivers/net/wireless/ath/ath9k/hw.c | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
> index 063d724..07dd330 100644
> --- a/drivers/net/wireless/ath/ath9k/hw.c
> +++ b/drivers/net/wireless/ath/ath9k/hw.c
> @@ -837,6 +837,9 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
>  		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
>  			      AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
>  		udelay(1000);
> +
> +		if (AR_SREV_9565(ah))
> +			REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x4142c);
>  	} else if (AR_SREV_9330(ah)) {
>  		u32 ddr_dpll2, pll_control2, kd;
>  
> @@ -917,9 +920,10 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
>  		udelay(1000);
>  	}
>  
> -	pll = ath9k_hw_compute_pll_control(ah, chan);
> -
> -	REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
> +	if (!AR_SREV_9565(ah)) {
> +		pll = ath9k_hw_compute_pll_control(ah, chan);
> +		REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
> +	}
That looks messed up, how about just:

	pll = ath9k_hw_compute_pll_control(ah, chan);
	if (AR_SREV_9565(ah))
		pll |= 0x40000;
	REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);

Or alternatively move that OR mask into ath9k_hw_compute_pll_control

- Felix
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diff mbox

Patch

diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 063d724..07dd330 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -837,6 +837,9 @@  static void ath9k_hw_init_pll(struct ath_hw *ah,
 		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
 			      AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
 		udelay(1000);
+
+		if (AR_SREV_9565(ah))
+			REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x4142c);
 	} else if (AR_SREV_9330(ah)) {
 		u32 ddr_dpll2, pll_control2, kd;
 
@@ -917,9 +920,10 @@  static void ath9k_hw_init_pll(struct ath_hw *ah,
 		udelay(1000);
 	}
 
-	pll = ath9k_hw_compute_pll_control(ah, chan);
-
-	REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
+	if (!AR_SREV_9565(ah)) {
+		pll = ath9k_hw_compute_pll_control(ah, chan);
+		REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
+	}
 
 	if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
 	    AR_SREV_9550(ah))