diff mbox

ath9k causes lockups since kernel 2.6.35

Message ID BANLkTik-DQxb8Ca698BeizRVyB71bWBndQ@mail.gmail.com (mailing list archive)
State Not Applicable, archived
Headers show

Commit Message

Adrian Chadd June 10, 2011, 6:48 a.m. UTC 
Hi all,

This patch against the current wireless-testing tree restores bit 6/7
being set for the AR9285.

Tony, would you please test this out and see if this works? This is
against the latest wireless-testing.

Thanks,


Adrian

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Comments

Stanislaw Gruszka June 13, 2011, 11 a.m. UTC | #1 
On Fri, Jun 10, 2011 at 02:48:00PM +0800, Adrian Chadd wrote:
> This patch against the current wireless-testing tree restores bit 6/7
> being set for the AR9285.
> 
> Tony, would you please test this out and see if this works? This is
> against the latest wireless-testing.

cam a fedora user, confirms that patch fixes the locks-ups
https://bugzilla.redhat.com/show_bug.cgi?id=697157#c26

We are waiting for fix now :-)

Thanks
Stanislaw
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diff mbox

Patch

diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
index f344cc2..5e4e37f 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -384,6 +384,7 @@  static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
                        }
                }

+#if 0
                if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
                        /*
                         * Disable bit 6 and 7 before entering D3 to
@@ -391,6 +392,7 @@  static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
                         */
                        val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
                }
+#endif

                if (AR_SREV_9280(ah))
                        val |= AR_WA_BIT22;
diff --git a/drivers/net/wireless/ath/ath9k/reg.h
b/drivers/net/wireless/ath/ath9k/reg.h
index c18ee99..a3c893d 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -704,7 +704,7 @@ 
 #define AR_WA_ANALOG_SHIFT              (1 << 20)
 #define AR_WA_POR_SHORT                 (1 << 21) /* PCI-E Phy reset control */
 #define AR_WA_BIT22                    (1 << 22)
-#define AR9285_WA_DEFAULT              0x004a050b
+#define AR9285_WA_DEFAULT              0x004a05cb
 #define AR9280_WA_DEFAULT              0x0040073b
 #define AR_WA_DEFAULT                  0x0000073f
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