diff mbox series

[2/7] wifi: rtw88: Fix download_firmware_validate() for RTL8814AU

Message ID a157faf6-16f4-41bd-a29f-0d8db7940e1b@gmail.com (mailing list archive)
State New
Delegated to: Ping-Ke Shih
Headers show
Series wifi: rtw88: Prepare to support RTL8814AU (part 1/2) | expand

Commit Message

Bitterblue Smith Jan. 26, 2025, 10:54 p.m. UTC
After the firmware is uploaded, download_firmware_validate() checks some
bits in REG_MCUFW_CTRL to see if everything went okay. The
RTL8814AU power on sequence sets bits 13 and 12 to 2, which this
function does not expect, so it thinks the firmware upload failed.

Make download_firmware_validate() ignore bits 13 and 12.

Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com>
---
 drivers/net/wireless/realtek/rtw88/reg.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Ping-Ke Shih Jan. 27, 2025, 6:21 a.m. UTC | #1
Bitterblue Smith <rtl8821cerfe2@gmail.com> wrote:
> After the firmware is uploaded, download_firmware_validate() checks some
> bits in REG_MCUFW_CTRL to see if everything went okay. The
> RTL8814AU power on sequence sets bits 13 and 12 to 2, which this
> function does not expect, so it thinks the firmware upload failed.
> 
> Make download_firmware_validate() ignore bits 13 and 12.
> 
> Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com>
> 

Acked-by: Ping-Ke Shih <pkshih@realtek.com>

Memo some traces from vendor driver:

For most chips, poll firmware ready by
   while (HALMAC_REG_R16(REG_MCUFW_CTRL) != 0xC078)
   
Other chips check ready by
   while ((HALMAC_REG_R16(REG_MCUFW_CTRL) & 0xC078) != 0xC078)

And, for all chips, BIT 12-13 are defined as CPU_CLK_SEL, so
I think this change is well.
diff mbox series

Patch

diff --git a/drivers/net/wireless/realtek/rtw88/reg.h b/drivers/net/wireless/realtek/rtw88/reg.h
index e438405fba56..209b6fc08a73 100644
--- a/drivers/net/wireless/realtek/rtw88/reg.h
+++ b/drivers/net/wireless/realtek/rtw88/reg.h
@@ -130,6 +130,7 @@ 
 #define BIT_SHIFT_ROM_PGE	16
 #define BIT_FW_INIT_RDY		BIT(15)
 #define BIT_FW_DW_RDY		BIT(14)
+#define BIT_CPU_CLK_SEL		(BIT(12) | BIT(13))
 #define BIT_RPWM_TOGGLE		BIT(7)
 #define BIT_RAM_DL_SEL		BIT(7)	/* legacy only */
 #define BIT_DMEM_CHKSUM_OK	BIT(6)
@@ -147,7 +148,7 @@ 
 				 BIT_CHECK_SUM_OK)
 #define FW_READY_LEGACY		(BIT_MCUFWDL_RDY | BIT_FWDL_CHK_RPT |	       \
 				 BIT_WINTINI_RDY | BIT_RAM_DL_SEL)
-#define FW_READY_MASK		0xffff
+#define FW_READY_MASK		(0xffff & ~BIT_CPU_CLK_SEL)
 
 #define REG_MCU_TST_CFG		0x84
 #define VAL_FW_TRIGGER		0x1