[PATCHv5,00/19] ARMv8.4-A Secure EL2

Message

Rémi Denis-Courmont Jan. 12, 2021, 10:44 a.m. UTC

Hi,

This adds Secure  EL2.

Changes since version 4:
- Fix NS unitialised in secure state stage 2 translation.
- Remove EEL2 translation block flag in 32-bit mode.
- Clarify comments on arm_is_el2_enabled().

----------------------------------------------------------------
Rémi Denis-Courmont (19):
      target/arm: remove redundant tests
      target/arm: add arm_is_el2_enabled() helper
      target/arm: use arm_is_el2_enabled() where applicable
      target/arm: use arm_hcr_el2_eff() where applicable
      target/arm: factor MDCR_EL2 common handling
      target/arm: declare new AA64PFR0 bit-fields
      target/arm: add 64-bit S-EL2 to EL exception table
      target/arm: add MMU stage 1 for Secure EL2
      target/arm: add ARMv8.4-SEL2 system registers
      target/arm: handle VMID change in secure state
      target/arm: do S1_ptw_translate() before address space lookup
      target/arm: translate NS bit in page-walks
      target/arm: generalize 2-stage page-walk condition
      target/arm: secure stage 2 translation regime
      target/arm: set HPFAR_EL2.NS on secure stage 2 faults
      target/arm: revector to run-time pick target EL
      target/arm: add ARMv8.4-SEL2 extension
      target/arm: enable Secure EL2 in max CPU
      target/arm: refactor vae1_tlbmask()

 target/arm/cpu-param.h     |   2 +-
 target/arm/cpu.c           |  10 +-
 target/arm/cpu.h           |  90 ++++++++--
 target/arm/cpu64.c         |   1 +
 target/arm/helper-a64.c    |   8 +-
 target/arm/helper.c        | 414 ++++++++++++++++++++++++++++++---------------
 target/arm/internals.h     |  36 ++++
 target/arm/op_helper.c     |   4 +-
 target/arm/tlb_helper.c    |   3 +
 target/arm/translate-a64.c |   4 +
 target/arm/translate.c     |  35 +++-
 11 files changed, 430 insertions(+), 177 deletions(-)

Comments

Peter Maydell Jan. 19, 2021, 11:13 a.m. UTC | #1

On Tue, 12 Jan 2021 at 10:59, Rémi Denis-Courmont
<[e-mail]> wrote:
>
>         Hi,
>
> This adds Secure  EL2.
>
> Changes since version 4:
> - Fix NS unitialised in secure state stage 2 translation.
> - Remove EEL2 translation block flag in 32-bit mode.
> - Clarify comments on arm_is_el2_enabled().

Looking through this patchset, it's practically ready and only
needs a couple of very tiny tweaks, so rather than asking you to
roll a v6, I'm just going to apply it to target-arm.next and
make the tweaks in the process:

 * patch 6 needed adjustment on rebase as commit 00a92832f4532
   has already added definitions of the ID_AA64PFR0 fields;
   I dropped the now-duplicate part of the patch and adjusted
   the commit message to match

 * patch 17: added the change requested by RTH:
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -2837,7 +2837,8 @@ static bool
msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
              */
             TCGv_i32 tcg_el;

-            if (dc_isar_feature(aa64_sel2, s)) {
+            if (arm_dc_feature(s, ARM_FEATURE_AARCH64) &&
+                dc_isar_feature(aa64_sel2, s)) {
                 /* Target EL is EL<3 minus SCR_EL3.EEL2> */
                 tcg_el = load_cpu_field(cp15.scr_el3);
                 tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1);

    and corrected the patch subject line to
    "target/arm: Implement SCR_EL2.EEL2"

thanks
-- PMM