| Message ID | 1565510821-3927-1-git-send-email-bmeng.cn@gmail.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | riscv: sifive_u: Improve the emulation fidelity of sifive_u machine | expand |
On Sun, Aug 11, 2019 at 4:07 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > As of today, the QEMU 'sifive_u' machine is a special target that does > not boot the upstream OpenSBI/U-Boot firmware images built for the real > SiFive HiFive Unleashed board. Hence OpenSBI supports a special platform > "qemu/sifive_u". For U-Boot, the sifive_fu540_defconfig is referenced > in the OpenSBI doc as its payload, but that does not boot at all due > to various issues in current QEMU 'sifive_u' machine codes. > > This series aims to improve the emulation fidelity of sifive_u machine, > so that the upstream OpenSBI, U-Boot and kernel images built for the > SiFive HiFive Unleashed board can be used out of the box without any > special hack. > > The major changes include: > - Heterogeneous harts creation supported, so that we can create a CPU > that exactly mirrors the real hardware: 1 E51 + 4 U54. > - Implemented a PRCI model for FU540 > - Implemented an OTP model for FU540, primarily used for storing serial > number of the board > - Fixed GEM support that was seriously broken on sifive_u > - Synced device tree with upstream Linux kernel on sifive_u > - Adding initramfs loading support on sifive_u > > OpenSBI v0.4 image built for sifive/fu540 is included as the default > bios image for 'sifive_u' machine. > > The series is tested against OpenSBI v0.4 image for sifive/fu540 > paltform, U-Boot v2019.10-rc1 image for sifive_fu540_defconfig, > and Linux kernel v5.3-rc3 image with the following patch: > > macb: Update compatibility string for SiFive FU540-C000 > https://patchwork.kernel.org/patch/11050003/ > > OpenSBI + U-Boot, ping/tftpboot with U-Boot MACB driver works well. > Boot Linux 64-bit defconfig image, verified that system console on > the serial 0 and ping host work pretty well. > > An OpenSBI patch was sent to drop the special "qemu/sifive_u" platform > support in OpenSBI. It will be applied after this QEMU series is merged. > http://lists.infradead.org/pipermail/opensbi/2019-August/000335.html > > Changes in v3: > - changed to use macros for management and compute cpu count > - use management cpu count + 1 for the min_cpus > - update IRQ numbers of both UARTs to match hardware as well > > Changes in v2: > - fixed the "interrupts-extended" property size > - update the file header to indicate at least 2 harts are created > - use create_unimplemented_device() to create the GEM management > block instead of sifive_mmio_emulate() > - add "phy-handle" property to the ethernet node > - keep the PLIC compatible string unchanged as OpenSBI uses that > for DT fix up > - drop patch "riscv: sifive: Move sifive_mmio_emulate() to a common place" > - new patch "riscv: sifive_e: Drop sifive_mmio_emulate()" > > Bin Meng (28): > riscv: hw: Remove superfluous "linux,phandle" property > riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell > riscv: Add a sifive_cpu.h to include both E and U cpu type defines > riscv: hart: Extract hart realize to a separate routine > riscv: hart: Support heterogeneous harts population > riscv: sifive_u: Update hart configuration to reflect the real FU540 > SoC > riscv: sifive_u: Set the minimum number of cpus to 2 > riscv: sifive_u: Update PLIC hart topology configuration string > riscv: sifive_u: Update UART base addresses and IRQs > riscv: sifive_u: Remove the unnecessary include of prci header > riscv: sifive: Rename sifive_prci.{c,h} to sifive_e_prci.{c,h} > riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming > riscv: sifive_e: prci: Update the PRCI register block size > riscv: sifive: Implement PRCI model for FU540 > riscv: sifive_u: Generate hfclk and rtcclk nodes > riscv: sifive_u: Add PRCI block to the SoC > riscv: sifive_u: Change UART node name in device tree > riscv: hw: Implement a model for SiFive FU540 OTP > riscv: sifive_u: Instantiate OTP memory with a serial number > riscv: roms: Update default bios for sifive_u machine > riscv: sifive_u: Update UART and ethernet node clock properties > riscv: sifive_u: Generate an aliases node in the device tree > riscv: sifive_u: Fix broken GEM support > riscv: sifive_u: Support loading initramfs > riscv: hw: Remove not needed PLIC properties in device tree > riscv: sifive_e: Drop sifive_mmio_emulate() > riscv: virt: Change create_fdt() to return void > riscv: sifive_u: Update model and compatible strings in device tree > I have no idea on why patch [20/28] and [26/28] failed to arrive on the mailing list. The "git send-email" logs said OK when these two patches were sent. In v2, these 2 patches are missing on patchwork, and unfortunately this is the same situation for v3. Attached these 2 patches. Regards, Bin
As of today, the QEMU 'sifive_u' machine is a special target that does not boot the upstream OpenSBI/U-Boot firmware images built for the real SiFive HiFive Unleashed board. Hence OpenSBI supports a special platform "qemu/sifive_u". For U-Boot, the sifive_fu540_defconfig is referenced in the OpenSBI doc as its payload, but that does not boot at all due to various issues in current QEMU 'sifive_u' machine codes. This series aims to improve the emulation fidelity of sifive_u machine, so that the upstream OpenSBI, U-Boot and kernel images built for the SiFive HiFive Unleashed board can be used out of the box without any special hack. The major changes include: - Heterogeneous harts creation supported, so that we can create a CPU that exactly mirrors the real hardware: 1 E51 + 4 U54. - Implemented a PRCI model for FU540 - Implemented an OTP model for FU540, primarily used for storing serial number of the board - Fixed GEM support that was seriously broken on sifive_u - Synced device tree with upstream Linux kernel on sifive_u - Adding initramfs loading support on sifive_u OpenSBI v0.4 image built for sifive/fu540 is included as the default bios image for 'sifive_u' machine. The series is tested against OpenSBI v0.4 image for sifive/fu540 paltform, U-Boot v2019.10-rc1 image for sifive_fu540_defconfig, and Linux kernel v5.3-rc3 image with the following patch: macb: Update compatibility string for SiFive FU540-C000 https://patchwork.kernel.org/patch/11050003/ OpenSBI + U-Boot, ping/tftpboot with U-Boot MACB driver works well. Boot Linux 64-bit defconfig image, verified that system console on the serial 0 and ping host work pretty well. An OpenSBI patch was sent to drop the special "qemu/sifive_u" platform support in OpenSBI. It will be applied after this QEMU series is merged. http://lists.infradead.org/pipermail/opensbi/2019-August/000335.html Changes in v3: - changed to use macros for management and compute cpu count - use management cpu count + 1 for the min_cpus - update IRQ numbers of both UARTs to match hardware as well Changes in v2: - fixed the "interrupts-extended" property size - update the file header to indicate at least 2 harts are created - use create_unimplemented_device() to create the GEM management block instead of sifive_mmio_emulate() - add "phy-handle" property to the ethernet node - keep the PLIC compatible string unchanged as OpenSBI uses that for DT fix up - drop patch "riscv: sifive: Move sifive_mmio_emulate() to a common place" - new patch "riscv: sifive_e: Drop sifive_mmio_emulate()" Bin Meng (28): riscv: hw: Remove superfluous "linux,phandle" property riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell riscv: Add a sifive_cpu.h to include both E and U cpu type defines riscv: hart: Extract hart realize to a separate routine riscv: hart: Support heterogeneous harts population riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC riscv: sifive_u: Set the minimum number of cpus to 2 riscv: sifive_u: Update PLIC hart topology configuration string riscv: sifive_u: Update UART base addresses and IRQs riscv: sifive_u: Remove the unnecessary include of prci header riscv: sifive: Rename sifive_prci.{c,h} to sifive_e_prci.{c,h} riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming riscv: sifive_e: prci: Update the PRCI register block size riscv: sifive: Implement PRCI model for FU540 riscv: sifive_u: Generate hfclk and rtcclk nodes riscv: sifive_u: Add PRCI block to the SoC riscv: sifive_u: Change UART node name in device tree riscv: hw: Implement a model for SiFive FU540 OTP riscv: sifive_u: Instantiate OTP memory with a serial number riscv: roms: Update default bios for sifive_u machine riscv: sifive_u: Update UART and ethernet node clock properties riscv: sifive_u: Generate an aliases node in the device tree riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Support loading initramfs riscv: hw: Remove not needed PLIC properties in device tree riscv: sifive_e: Drop sifive_mmio_emulate() riscv: virt: Change create_fdt() to return void riscv: sifive_u: Update model and compatible strings in device tree hw/riscv/Makefile.objs | 4 +- hw/riscv/riscv_hart.c | 75 ++++++-- hw/riscv/sifive_e.c | 27 ++- hw/riscv/{sifive_prci.c => sifive_e_prci.c} | 16 +- hw/riscv/sifive_u.c | 185 ++++++++++++++------ hw/riscv/sifive_u_otp.c | 194 +++++++++++++++++++++ hw/riscv/sifive_u_prci.c | 163 +++++++++++++++++ hw/riscv/virt.c | 40 ++--- include/hw/riscv/sifive_cpu.h | 31 ++++ include/hw/riscv/sifive_e.h | 7 +- .../hw/riscv/{sifive_prci.h => sifive_e_prci.h} | 16 +- include/hw/riscv/sifive_u.h | 22 +-- include/hw/riscv/sifive_u_otp.h | 90 ++++++++++ include/hw/riscv/sifive_u_prci.h | 100 +++++++++++ pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 40968 -> 45064 bytes roms/Makefile | 4 +- 16 files changed, 830 insertions(+), 144 deletions(-) rename hw/riscv/{sifive_prci.c => sifive_e_prci.c} (88%) create mode 100644 hw/riscv/sifive_u_otp.c create mode 100644 hw/riscv/sifive_u_prci.c create mode 100644 include/hw/riscv/sifive_cpu.h rename include/hw/riscv/{sifive_prci.h => sifive_e_prci.h} (80%) create mode 100644 include/hw/riscv/sifive_u_otp.h create mode 100644 include/hw/riscv/sifive_u_prci.h