| Message ID | 20181010203735.27918-1-aclindsa@gmail.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | More fully implement ARM PMUv3 | expand |
On 10 October 2018 at 21:37, Aaron Lindsay <aclindsa@gmail.com> wrote: > The ARM PMU implementation currently contains a basic cycle counter, but > it is often useful to gather counts of other events, filter them based > on execution mode, and/or be notified on counter overflow. These patches > flesh out the implementations of various PMU registers including > PM[X]EVCNTR and PM[X]EVTYPER, add a struct definition to represent > arbitrary counter types, implement mode filtering, send interrupts on > counter overflow, and add instruction, cycle, and software increment > events. > > Since v5 [1] I have: > * Taken a first pass at addressing migration > * Restructured the list of supported events, and ensured they're all > initialized > * Fixed aliasing for PMOVSSET > * Added ARM_CP_IO for PMINTENCLR and PMINTENCLR_EL1 > * Addressed a few non-code issues (comment style, patch staging, > spelling, etc.) > > [1] - https://lists.gnu.org/archive/html/qemu-devel/2018-06/msg06830.html > > Aaron Lindsay (14): > target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly > doing IO > target/arm: Mask PMOVSR writes based on supported counters Hi; Richard has reviewed most of this series and suggested some changes (thanks!); I'll just take these first two patches into target-arm.next, since they're simple fixes that have been reviewed. thanks -- PMM
On Oct 16 13:01, Peter Maydell wrote: > On 10 October 2018 at 21:37, Aaron Lindsay <aclindsa@gmail.com> wrote: > > The ARM PMU implementation currently contains a basic cycle counter, but > > it is often useful to gather counts of other events, filter them based > > on execution mode, and/or be notified on counter overflow. These patches > > flesh out the implementations of various PMU registers including > > PM[X]EVCNTR and PM[X]EVTYPER, add a struct definition to represent > > arbitrary counter types, implement mode filtering, send interrupts on > > counter overflow, and add instruction, cycle, and software increment > > events. > > > > Since v5 [1] I have: > > * Taken a first pass at addressing migration > > * Restructured the list of supported events, and ensured they're all > > initialized > > * Fixed aliasing for PMOVSSET > > * Added ARM_CP_IO for PMINTENCLR and PMINTENCLR_EL1 > > * Addressed a few non-code issues (comment style, patch staging, > > spelling, etc.) > > > > [1] - https://lists.gnu.org/archive/html/qemu-devel/2018-06/msg06830.html > > > > Aaron Lindsay (14): > > target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly > > doing IO > > target/arm: Mask PMOVSR writes based on supported counters > > Hi; Richard has reviewed most of this series and suggested some > changes (thanks!); I'll just take these first two patches into > target-arm.next, since they're simple fixes that have been reviewed. Thanks, Peter and Richard! Is anyone willing to take a glance at the final patch in this series, "target/arm: Send interrupts on PMU counter overflow", before my next iteration? I'm particularly interested in a review of the approach I took for detecting overflow. -Aaron
On 10/16/18 5:46 AM, Aaron Lindsay wrote: > Is anyone willing to take a glance at the final patch in this series, > "target/arm: Send interrupts on PMU counter overflow", before my next > iteration? I'm particularly interested in a review of the approach I > took for detecting overflow. I intend to finish reviewing the patch series today. r~
The ARM PMU implementation currently contains a basic cycle counter, but it is often useful to gather counts of other events, filter them based on execution mode, and/or be notified on counter overflow. These patches flesh out the implementations of various PMU registers including PM[X]EVCNTR and PM[X]EVTYPER, add a struct definition to represent arbitrary counter types, implement mode filtering, send interrupts on counter overflow, and add instruction, cycle, and software increment events. Since v5 [1] I have: * Taken a first pass at addressing migration * Restructured the list of supported events, and ensured they're all initialized * Fixed aliasing for PMOVSSET * Added ARM_CP_IO for PMINTENCLR and PMINTENCLR_EL1 * Addressed a few non-code issues (comment style, patch staging, spelling, etc.) [1] - https://lists.gnu.org/archive/html/qemu-devel/2018-06/msg06830.html Aaron Lindsay (14): target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO target/arm: Mask PMOVSR writes based on supported counters migration: Add post_save function to VMStateDescription target/arm: Swap PMU values before/after migrations target/arm: Reorganize PMCCNTR accesses target/arm: Filter cycle counter based on PMCCFILTR_EL0 target/arm: Allow AArch32 access for PMCCFILTR target/arm: Implement PMOVSSET target/arm: Add array for supported PMU events, generate PMCEID[01] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER target/arm: PMU: Add instruction and cycle events target/arm: PMU: Set PMCR.N to 4 target/arm: Implement PMSWINC target/arm: Send interrupts on PMU counter overflow docs/devel/migration.rst | 9 +- include/migration/vmstate.h | 1 + migration/vmstate.c | 10 +- target/arm/cpu.c | 28 +- target/arm/cpu.h | 68 +++- target/arm/cpu64.c | 2 - target/arm/helper.c | 781 ++++++++++++++++++++++++++++++++---- target/arm/machine.c | 19 + 8 files changed, 817 insertions(+), 101 deletions(-)