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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id jx4sm13519070pjb.24.2021.01.10.00.15.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jan 2021 00:15:13 -0800 (PST) From: Bin Meng <bmeng.cn@gmail.com> To: Peter Maydell <peter.maydell@linaro.org>, Jean-Christophe Dubois <jcd@tribudubois.net>, Alistair Francis <alistair.francis@wdc.com>, =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= <f4bug@amsat.org>, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v4 0/6] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Date: Sun, 10 Jan 2021 16:14:23 +0800 Message-Id: <20210110081429.10126-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: Bin Meng <bin.meng@windriver.com> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> |
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hw/ssi: imx_spi: Fix various bugs in the imx_spi model
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From: Bin Meng <bin.meng@windriver.com> This series fixes a bunch of bugs in current implementation of the imx spi controller, including the following issues: - chip select signal was not lower down when spi controller is disabled - remove imx_spi_update_irq() in imx_spi_reset() - transfer incorrect data when the burst length is larger than 32 bit - spi controller tx and rx fifo endianness is incorrect Tested with upstream U-Boot v2020.10 (polling mode) and VxWorks 7 (interrupt mode). Changes in v4: - adujst the patch 2,3 order - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion - s/normal/common/ in the commit message - log the burst length value in the log message Changes in v3: - new patch: remove imx_spi_update_irq() in imx_spi_reset() - Move the chip selects disable out of imx_spi_reset() - new patch: log unimplemented burst length - Simplify the tx fifo endianness handling Changes in v2: - Fix the "Fixes" tag in the commit message - Use ternary operator as Philippe suggested Bin Meng (5): hw/ssi: imx_spi: Use a macro for number of chip selects supported hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() hw/ssi: imx_spi: Log unimplemented burst length hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic hw/ssi: imx_spi: Correct tx and rx fifo endianness Xuzhou Cheng (1): hw/ssi: imx_spi: Disable chip selects when controller is disabled include/hw/ssi/imx_spi.h | 5 ++++- hw/ssi/imx_spi.c | 42 ++++++++++++++++++++++++++++------------ 2 files changed, 34 insertions(+), 13 deletions(-)