| Message ID | 20210510190844.17799-1-peter.maydell@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | hw/arm: Fix modelling of SSE-300 TCMs and SRAM | expand |
Hi Peter, On 5/10/21 9:08 PM, Peter Maydell wrote: > This patchset fixes some bugs in how we were modelling the > TCMs and the SRAM in the SSE-300 which were preventing > Arm TF-M from booting on our AN547 model; there are also > some fixes to things I noticed while I was in the code. > > The specific bugs preventing boot were: > * SRAM_ADDR_WIDTH for the AN547 is 21, not 15, so the SRAM > area was too small > * we were putting the SRAMs at the wrong address (0x2100_0000 > for SSE-300, not 0x2000_0000 as for SSE-200) How can we test it? > The other stuff I've fixed is: > * we were modelling the SRAM in the AN524 both in the SSE > and in the board model (harmlessly, as the board-model > memory was just always shadowed in the memory map and > unreachable) > * we were modelling the TCMs in the AN547 board model, > which is conceptually wrong because in hardware they're > part of the SSE-300. No guest-visible change, but it will > avoid problems if/when we add another SSE-300 board model > > thanks > -- PMM > > Peter Maydell (6): > hw/arm/mps2-tz: Don't duplicate modelling of SRAM in AN524 > hw/arm/mps2-tz: Make SRAM_ADDR_WIDTH board-specific > hw/arm/armsse.c: Correct modelling of SSE-300 internal SRAMs > hw/arm/armsse: Convert armsse_realize() to use ERRP_GUARD > hw/arm/mps2-tz: Allow board to specify a boot RAM size > hw/arm: Model TCMs in the SSE-300, not the AN547 > > include/hw/arm/armsse.h | 2 ++ > hw/arm/armsse.c | 35 +++++++++++++++++++++++++++++------ > hw/arm/mps2-tz.c | 39 ++++++++++++++++++++------------------- > 3 files changed, 51 insertions(+), 25 deletions(-) >
On Mon, 10 May 2021 at 20:14, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote: > > Hi Peter, > > On 5/10/21 9:08 PM, Peter Maydell wrote: > > This patchset fixes some bugs in how we were modelling the > > TCMs and the SRAM in the SSE-300 which were preventing > > Arm TF-M from booting on our AN547 model; there are also > > some fixes to things I noticed while I was in the code. > > > > The specific bugs preventing boot were: > > * SRAM_ADDR_WIDTH for the AN547 is 21, not 15, so the SRAM > > area was too small > > * we were putting the SRAMs at the wrong address (0x2100_0000 > > for SSE-300, not 0x2000_0000 as for SSE-200) > > How can we test it? I tested using a binary that Devaraj provided me. As usual, I don't know if there's anything that would be a sufficiently "publicly hosted, with associated source for licensing purposes" binary that we could put into tests/acceptance. -- PMM
On 5/10/21 9:22 PM, Peter Maydell wrote: > On Mon, 10 May 2021 at 20:14, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote: >> >> Hi Peter, >> >> On 5/10/21 9:08 PM, Peter Maydell wrote: >>> This patchset fixes some bugs in how we were modelling the >>> TCMs and the SRAM in the SSE-300 which were preventing >>> Arm TF-M from booting on our AN547 model; there are also >>> some fixes to things I noticed while I was in the code. >>> >>> The specific bugs preventing boot were: >>> * SRAM_ADDR_WIDTH for the AN547 is 21, not 15, so the SRAM >>> area was too small >>> * we were putting the SRAMs at the wrong address (0x2100_0000 >>> for SSE-300, not 0x2000_0000 as for SSE-200) >> >> How can we test it? > > I tested using a binary that Devaraj provided me. As usual, > I don't know if there's anything that would be a sufficiently > "publicly hosted, with associated source for licensing purposes" > binary that we could put into tests/acceptance. OK, thank you. Phil.
On Mon, 10 May 2021 at 20:08, Peter Maydell <peter.maydell@linaro.org> wrote: > > This patchset fixes some bugs in how we were modelling the > TCMs and the SRAM in the SSE-300 which were preventing > Arm TF-M from booting on our AN547 model; there are also > some fixes to things I noticed while I was in the code. > > The specific bugs preventing boot were: > * SRAM_ADDR_WIDTH for the AN547 is 21, not 15, so the SRAM > area was too small > * we were putting the SRAMs at the wrong address (0x2100_0000 > for SSE-300, not 0x2000_0000 as for SSE-200) > > The other stuff I've fixed is: > * we were modelling the SRAM in the AN524 both in the SSE > and in the board model (harmlessly, as the board-model > memory was just always shadowed in the memory map and > unreachable) > * we were modelling the TCMs in the AN547 board model, > which is conceptually wrong because in hardware they're > part of the SSE-300. No guest-visible change, but it will > avoid problems if/when we add another SSE-300 board model > > thanks > -- PMM Ping for code review, please? thanks -- PMM