mbox series

[v3,0/3] Support 64-bit address of initrd

Message ID 20241108070454.12699-1-jim.shu@sifive.com (mailing list archive)
Headers show
Series Support 64-bit address of initrd | expand

Message

Jim Shu Nov. 8, 2024, 7:04 a.m. UTC
Support to load DTB after 3GB on RV64 system, so that larger initrd
doesn't be overlapped to DTB. DTB loading now will check if overlapping
to kernel/initrd and report this error.

Verify the patch via running 4GB initramfs on the virt machine.

Changes for v3:

  - Change struct RISCVBootInfo from machine state to local variables.

Changes for v2:

  - Add DTB overlapping checking and struct RISCVBootInfo
  - Remove the commit to change #address-cell of 'initrd-[start|end]'

Jim Shu (3):
  hw/riscv: Support to load DTB after 3GB memory on 64-bit system.
  hw/riscv: Add a new struct RISCVBootInfo
  hw/riscv: Add the checking if DTB overlaps to kernel or initrd

 hw/riscv/boot.c                    | 94 +++++++++++++++++++++---------
 hw/riscv/microchip_pfsoc.c         | 14 +++--
 hw/riscv/opentitan.c               |  5 +-
 hw/riscv/sifive_e.c                |  5 +-
 hw/riscv/sifive_u.c                | 15 ++---
 hw/riscv/spike.c                   | 15 ++---
 hw/riscv/virt.c                    | 14 +++--
 include/hw/riscv/boot.h            | 28 ++++++---
 include/hw/riscv/microchip_pfsoc.h |  1 +
 include/hw/riscv/opentitan.h       |  1 +
 include/hw/riscv/sifive_e.h        |  1 +
 include/hw/riscv/sifive_u.h        |  1 +
 include/hw/riscv/spike.h           |  1 +
 include/hw/riscv/virt.h            |  1 +
 14 files changed, 130 insertions(+), 66 deletions(-)