[10.1,v3,00/27] target/riscv: SATP mode and CPU definition overhaul

Message

Paolo Bonzini April 6, 2025, 7:02 a.m. UTC

This is the combination of the previously posted series to store max SATP
mode in RISCVCPUConfig as a single integer, and convert CPU definitions
to a small extension of RISCVCPUConfig called RISCVCPUDef.  I put them
together because the first part (patches 1-6) is already acked/reviewed.

As mentioned in the earlier submissions, the main reason for me to do this
is to remove .instance_post_init, which RISC-V is using in a slightly different
way than everyone else.  Whereas other uses (including x86, which is
currently buggy, and Rust) would prefer to call .instance_post_init
from root to leaf, RISC-V needs it to be called from leaf (CPU model)
to parent (DeviceState).  The fix is to move the logic of the former
.instance_post_init callback for the leaf at the end of the leaf's
.instance_init, as done in this series.

Paolo

Supersedes: <[e-mail]>

Paolo Bonzini (27):
  hw/riscv: acpi: only create RHCT MMU entry for supported types
  target/riscv: assert argument to set_satp_mode_max_supported is valid
  target/riscv: cpu: store max SATP mode as a single integer
  target/riscv: update max_satp_mode based on QOM properties
  target/riscv: remove supported from RISCVSATPMap
  target/riscv: move satp_mode.{map,init} out of CPUConfig
  target/riscv: introduce RISCVCPUDef
  target/riscv: store RISCVCPUDef struct directly in the class
  target/riscv: merge riscv_cpu_class_init with the class_base function
  target/riscv: move RISCVCPUConfig fields to a header file
  target/riscv: include default value in cpu_cfg_fields.h.inc
  target/riscv: do not make RISCVCPUConfig fields conditional
  target/riscv: add more RISCVCPUDef fields
  target/riscv: convert abstract CPU classes to RISCVCPUDef
  target/riscv: convert profile CPU models to RISCVCPUDef
  target/riscv: convert bare CPU models to RISCVCPUDef
  target/riscv: convert dynamic CPU models to RISCVCPUDef
  target/riscv: convert SiFive E CPU models to RISCVCPUDef
  target/riscv: convert ibex CPU models to RISCVCPUDef
  target/riscv: convert SiFive U models to RISCVCPUDef
  target/riscv: th: make CSR insertion test a bit more intuitive
  target/riscv: generalize custom CSR functionality
  target/riscv: convert TT C906 to RISCVCPUDef
  target/riscv: convert TT Ascalon to RISCVCPUDef
  target/riscv: convert Ventana V1 to RISCVCPUDef
  target/riscv: convert Xiangshan Nanhu to RISCVCPUDef
  target/riscv: remove .instance_post_init

 target/riscv/cpu-qom.h            |    2 +
 target/riscv/cpu.h                |   42 +-
 target/riscv/cpu_cfg.h            |  180 +----
 target/riscv/cpu_cfg_fields.h.inc |  170 +++++
 hw/riscv/boot.c                   |    2 +-
 hw/riscv/virt-acpi-build.c        |   15 +-
 hw/riscv/virt.c                   |    5 +-
 target/riscv/cpu.c                | 1014 +++++++++++++----------------
 target/riscv/csr.c                |   11 +-
 target/riscv/gdbstub.c            |    6 +-
 target/riscv/kvm/kvm-cpu.c        |   27 +-
 target/riscv/machine.c            |    2 +-
 target/riscv/tcg/tcg-cpu.c        |   13 +-
 target/riscv/th_csr.c             |   30 +-
 target/riscv/translate.c          |    2 +-
 15 files changed, 729 insertions(+), 792 deletions(-)
 create mode 100644 target/riscv/cpu_cfg_fields.h.inc