Show patches with: Series = target/riscv: SATP mode and CPU definition overhaul       |    State = Action Required       |    Archived = No       |   27 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[27/27] target/riscv: remove .instance_post_init target/riscv: SATP mode and CPU definition overhaul - - - --- 2025-04-06 Paolo Bonzini New
[26/27] target/riscv: convert Xiangshan Nanhu to RISCVCPUDef target/riscv: SATP mode and CPU definition overhaul - - - --- 2025-04-06 Paolo Bonzini New
[25/27] target/riscv: convert Ventana V1 to RISCVCPUDef target/riscv: SATP mode and CPU definition overhaul - - - --- 2025-04-06 Paolo Bonzini New
[24/27] target/riscv: convert TT Ascalon to RISCVCPUDef target/riscv: SATP mode and CPU definition overhaul - - - --- 2025-04-06 Paolo Bonzini New
[23/27] target/riscv: convert TT C906 to RISCVCPUDef target/riscv: SATP mode and CPU definition overhaul - - - --- 2025-04-06 Paolo Bonzini New
[22/27] target/riscv: generalize custom CSR functionality target/riscv: SATP mode and CPU definition overhaul - - - --- 2025-04-06 Paolo Bonzini New
[21/27] target/riscv: th: make CSR insertion test a bit more intuitive target/riscv: SATP mode and CPU definition overhaul - - - --- 2025-04-06 Paolo Bonzini New
[20/27] target/riscv: convert SiFive U models to RISCVCPUDef target/riscv: SATP mode and CPU definition overhaul - - - --- 2025-04-06 Paolo Bonzini New
[19/27] target/riscv: convert ibex CPU models to RISCVCPUDef target/riscv: SATP mode and CPU definition overhaul - - - --- 2025-04-06 Paolo Bonzini New
[18/27] target/riscv: convert SiFive E CPU models to RISCVCPUDef target/riscv: SATP mode and CPU definition overhaul - - - --- 2025-04-06 Paolo Bonzini New
[17/27] target/riscv: convert dynamic CPU models to RISCVCPUDef target/riscv: SATP mode and CPU definition overhaul - - - --- 2025-04-06 Paolo Bonzini New
[16/27] target/riscv: convert bare CPU models to RISCVCPUDef target/riscv: SATP mode and CPU definition overhaul - - - --- 2025-04-06 Paolo Bonzini New
[15/27] target/riscv: convert profile CPU models to RISCVCPUDef target/riscv: SATP mode and CPU definition overhaul - - - --- 2025-04-06 Paolo Bonzini New
[14/27] target/riscv: convert abstract CPU classes to RISCVCPUDef target/riscv: SATP mode and CPU definition overhaul - - - --- 2025-04-06 Paolo Bonzini New
[13/27] target/riscv: add more RISCVCPUDef fields target/riscv: SATP mode and CPU definition overhaul - - - --- 2025-04-06 Paolo Bonzini New
[12/27] target/riscv: do not make RISCVCPUConfig fields conditional target/riscv: SATP mode and CPU definition overhaul - - - --- 2025-04-06 Paolo Bonzini New
[11/27] target/riscv: include default value in cpu_cfg_fields.h.inc target/riscv: SATP mode and CPU definition overhaul - - - --- 2025-04-06 Paolo Bonzini New
[10/27] target/riscv: move RISCVCPUConfig fields to a header file target/riscv: SATP mode and CPU definition overhaul - 1 - --- 2025-04-06 Paolo Bonzini New
[09/27] target/riscv: merge riscv_cpu_class_init with the class_base function target/riscv: SATP mode and CPU definition overhaul - 1 - --- 2025-04-06 Paolo Bonzini New
[08/27] target/riscv: store RISCVCPUDef struct directly in the class target/riscv: SATP mode and CPU definition overhaul - 1 - --- 2025-04-06 Paolo Bonzini New
[07/27] target/riscv: introduce RISCVCPUDef target/riscv: SATP mode and CPU definition overhaul - 1 - --- 2025-04-06 Paolo Bonzini New
[06/27] target/riscv: move satp_mode.{map, init} out of CPUConfig target/riscv: SATP mode and CPU definition overhaul - 1 - --- 2025-04-06 Paolo Bonzini New
[05/27] target/riscv: remove supported from RISCVSATPMap target/riscv: SATP mode and CPU definition overhaul - 1 - --- 2025-04-06 Paolo Bonzini New
[04/27] target/riscv: update max_satp_mode based on QOM properties target/riscv: SATP mode and CPU definition overhaul - 1 - --- 2025-04-06 Paolo Bonzini New
[03/27] target/riscv: cpu: store max SATP mode as a single integer target/riscv: SATP mode and CPU definition overhaul - 1 - --- 2025-04-06 Paolo Bonzini New
[02/27] target/riscv: assert argument to set_satp_mode_max_supported is valid target/riscv: SATP mode and CPU definition overhaul - 1 - --- 2025-04-06 Paolo Bonzini New
[01/27] hw/riscv: acpi: only create RHCT MMU entry for supported types target/riscv: SATP mode and CPU definition overhaul 1 - - --- 2025-04-06 Paolo Bonzini New