[for,4.0,v1,0/5] Update the QEMU PLIC addresses

Message

Alistair Francis March 21, 2019, 12:45 a.m. UTC

This series updates the PLIC address to match the documentation.

This fixes: https://github.com/riscv/opensbi/issues/97

Alistair Francis (5):
  riscv: plic: Fix incorrect irq calculation
  riscv: sifive_u: Fix PLIC priority base offset and numbering
  riscv: sifive_e: Fix PLIC priority base offset
  riscv: virt: Fix PLIC priority base offset
  riscv: plic: Log guest errors

 hw/riscv/sifive_plic.c      | 16 +++++++++++-----
 hw/riscv/sifive_u.c         |  2 +-
 include/hw/riscv/sifive_e.h |  2 +-
 include/hw/riscv/sifive_u.h |  4 ++--
 include/hw/riscv/virt.h     |  2 +-
 5 files changed, 16 insertions(+), 10 deletions(-)

Comments

Alistair Francis March 26, 2019, 10:19 p.m. UTC | #1

On Wed, Mar 20, 2019 at 5:45 PM Alistair Francis
<[e-mail]> wrote:
>
> This series updates the PLIC address to match the documentation.
>
> This fixes: https://github.com/riscv/opensbi/issues/97
>
> Alistair Francis (5):
>   riscv: plic: Fix incorrect irq calculation
>   riscv: sifive_u: Fix PLIC priority base offset and numbering
>   riscv: sifive_e: Fix PLIC priority base offset
>   riscv: virt: Fix PLIC priority base offset
>   riscv: plic: Log guest errors

Ping! Can this make it into 4.0?

Alistair

>
>  hw/riscv/sifive_plic.c      | 16 +++++++++++-----
>  hw/riscv/sifive_u.c         |  2 +-
>  include/hw/riscv/sifive_e.h |  2 +-
>  include/hw/riscv/sifive_u.h |  4 ++--
>  include/hw/riscv/virt.h     |  2 +-
>  5 files changed, 16 insertions(+), 10 deletions(-)
>
> --
> 2.21.0
>

Philippe Mathieu-Daudé March 26, 2019, 11:23 p.m. UTC | #2

Le jeu. 21 mars 2019 02:00, Alistair Francis <[e-mail]> a
écrit :

> Instead of using error_report() to print guest errors let's use
> qemu_log_mask(LOG_GUEST_ERROR,...) to log the error.
>
> Signed-off-by: Alistair Francis <[e-mail]>
> ---
>  hw/riscv/sifive_plic.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
> index 70a85cd075..7f373d6c9d 100644
> --- a/hw/riscv/sifive_plic.c
> +++ b/hw/riscv/sifive_plic.c
> @@ -262,7 +262,9 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr
> addr, unsigned size)
>      }
>
>  err:
> -    error_report("plic: invalid register read: %08x", (uint32_t)addr);
> +    qemu_log_mask(LOG_GUEST_ERROR,
> +                  "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
> +                  __func__, addr);
>      return 0;
>  }
>
> @@ -289,7 +291,9 @@ static void sifive_plic_write(void *opaque, hwaddr
> addr, uint64_t value,
>      } else if (addr >= plic->pending_base && /* 1 bit per source */
>                 addr < plic->pending_base + (plic->num_sources >> 3))
>      {
> -        error_report("plic: invalid pending write: %08x", (uint32_t)addr);
> +        qemu_log_mask(LOG_GUEST_ERROR,
> +                      "%s: invalid pending write: 0x%" HWADDR_PRIx "",
> +                      __func__, addr);
>          return;
>      } else if (addr >= plic->enable_base && /* 1 bit per source */
>          addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
> @@ -339,7 +343,9 @@ static void sifive_plic_write(void *opaque, hwaddr
> addr, uint64_t value,
>      }
>
>  err:
> -    error_report("plic: invalid register write: %08x", (uint32_t)addr);
> +    qemu_log_mask(LOG_GUEST_ERROR,
> +                  "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
> +                  __func__, addr);
>  }
>
>  static const MemoryRegionOps sifive_plic_ops = {
> --
> 2.21.0
>

Reviewed-by: Philippe Mathieu-Daudé <[e-mail]>

>

Palmer Dabbelt March 27, 2019, 6:14 a.m. UTC | #3

On Tue, 26 Mar 2019 15:19:25 PDT (-0700), [e-mail] wrote:
> On Wed, Mar 20, 2019 at 5:45 PM Alistair Francis
> <[e-mail]> wrote:
>>
>> This series updates the PLIC address to match the documentation.
>>
>> This fixes: https://github.com/riscv/opensbi/issues/97
>>
>> Alistair Francis (5):
>>   riscv: plic: Fix incorrect irq calculation
>>   riscv: sifive_u: Fix PLIC priority base offset and numbering
>>   riscv: sifive_e: Fix PLIC priority base offset
>>   riscv: virt: Fix PLIC priority base offset
>>   riscv: plic: Log guest errors
>
> Ping! Can this make it into 4.0?

Sorry, I missed this one.  I'll take a look.

>
> Alistair
>
>>
>>  hw/riscv/sifive_plic.c      | 16 +++++++++++-----
>>  hw/riscv/sifive_u.c         |  2 +-
>>  include/hw/riscv/sifive_e.h |  2 +-
>>  include/hw/riscv/sifive_u.h |  4 ++--
>>  include/hw/riscv/virt.h     |  2 +-
>>  5 files changed, 16 insertions(+), 10 deletions(-)
>>
>> --
>> 2.21.0
>>