mbox series

[for,4.0,v2,0/2] Update the QEMU PLIC addresses

Message ID cover.1553712571.git.alistair.francis@wdc.com (mailing list archive)
Headers show
Series Update the QEMU PLIC addresses | expand

Message

Alistair Francis March 27, 2019, 6:51 p.m. UTC
This series updates the PLIC address to match the documentation.

This fixes: https://github.com/riscv/opensbi/issues/97

V2:
 - Squash patches to ensure biesctability

Alistair Francis (2):
  riscv: plic: Fix incorrect irq calculation
  riscv: plic: Log guest errors

 hw/riscv/sifive_plic.c      | 16 +++++++++++-----
 hw/riscv/sifive_u.c         |  2 +-
 include/hw/riscv/sifive_e.h |  2 +-
 include/hw/riscv/sifive_u.h |  4 ++--
 include/hw/riscv/virt.h     |  2 +-
 5 files changed, 16 insertions(+), 10 deletions(-)

Comments

Philippe Mathieu-Daudé March 27, 2019, 10:02 p.m. UTC | #1
Le mer. 27 mars 2019 19:57, Alistair Francis <Alistair.Francis@wdc.com> a
écrit :

> Instead of using error_report() to print guest errors let's use
> qemu_log_mask(LOG_GUEST_ERROR,...) to log the error.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  hw/riscv/sifive_plic.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
> index 70a85cd075..7f373d6c9d 100644
> --- a/hw/riscv/sifive_plic.c
> +++ b/hw/riscv/sifive_plic.c
> @@ -262,7 +262,9 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr
> addr, unsigned size)
>      }
>
>  err:
> -    error_report("plic: invalid register read: %08x", (uint32_t)addr);
> +    qemu_log_mask(LOG_GUEST_ERROR,
> +                  "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
> +                  __func__, addr);
>      return 0;
>  }
>
> @@ -289,7 +291,9 @@ static void sifive_plic_write(void *opaque, hwaddr
> addr, uint64_t value,
>      } else if (addr >= plic->pending_base && /* 1 bit per source */
>                 addr < plic->pending_base + (plic->num_sources >> 3))
>      {
> -        error_report("plic: invalid pending write: %08x", (uint32_t)addr);
> +        qemu_log_mask(LOG_GUEST_ERROR,
> +                      "%s: invalid pending write: 0x%" HWADDR_PRIx "",
> +                      __func__, addr);
>          return;
>      } else if (addr >= plic->enable_base && /* 1 bit per source */
>          addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
> @@ -339,7 +343,9 @@ static void sifive_plic_write(void *opaque, hwaddr
> addr, uint64_t value,
>      }
>
>  err:
> -    error_report("plic: invalid register write: %08x", (uint32_t)addr);
> +    qemu_log_mask(LOG_GUEST_ERROR,
> +                  "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
> +                  __func__, addr);
>  }
>
>  static const MemoryRegionOps sifive_plic_ops = {
> --
> 2.21.0
>

I'm using the GMail embedded gapp and wonder if the deduplication features
is not sometimes abusive, when the same patch is sent increasing versions,
I reply to the last version I see but my reply looks like I replied to the
first.
I might be also misusing the gapp :)
Anyway:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

>
Palmer Dabbelt March 28, 2019, 3:23 a.m. UTC | #2
On Wed, 27 Mar 2019 11:51:15 PDT (-0700), Alistair Francis wrote:
> This series updates the PLIC address to match the documentation.
>
> This fixes: https://github.com/riscv/opensbi/issues/97
>
> V2:
>  - Squash patches to ensure biesctability
>
> Alistair Francis (2):
>   riscv: plic: Fix incorrect irq calculation
>   riscv: plic: Log guest errors
>
>  hw/riscv/sifive_plic.c      | 16 +++++++++++-----
>  hw/riscv/sifive_u.c         |  2 +-
>  include/hw/riscv/sifive_e.h |  2 +-
>  include/hw/riscv/sifive_u.h |  4 ++--
>  include/hw/riscv/virt.h     |  2 +-
>  5 files changed, 16 insertions(+), 10 deletions(-)
>
> -- 
> 2.21.0

Thanks, I've got these on for-master.  I'll let them sit for a bit to see if 
there are any other comments, but

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Alistair Francis April 3, 2019, 11:32 p.m. UTC | #3
On Wed, Mar 27, 2019 at 8:23 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Wed, 27 Mar 2019 11:51:15 PDT (-0700), Alistair Francis wrote:
> > This series updates the PLIC address to match the documentation.
> >
> > This fixes: https://github.com/riscv/opensbi/issues/97
> >
> > V2:
> >  - Squash patches to ensure biesctability
> >
> > Alistair Francis (2):
> >   riscv: plic: Fix incorrect irq calculation
> >   riscv: plic: Log guest errors
> >
> >  hw/riscv/sifive_plic.c      | 16 +++++++++++-----
> >  hw/riscv/sifive_u.c         |  2 +-
> >  include/hw/riscv/sifive_e.h |  2 +-
> >  include/hw/riscv/sifive_u.h |  4 ++--
> >  include/hw/riscv/virt.h     |  2 +-
> >  5 files changed, 16 insertions(+), 10 deletions(-)
> >
> > --
> > 2.21.0
>
> Thanks, I've got these on for-master.  I'll let them sit for a bit to see if
> there are any other comments, but
>
> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Ping! Just want to make sure these make it into 4.0

Alistair
Palmer Dabbelt April 4, 2019, 1 a.m. UTC | #4
On Wed, 03 Apr 2019 16:32:11 PDT (-0700), alistair23@gmail.com wrote:
> On Wed, Mar 27, 2019 at 8:23 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>>
>> On Wed, 27 Mar 2019 11:51:15 PDT (-0700), Alistair Francis wrote:
>> > This series updates the PLIC address to match the documentation.
>> >
>> > This fixes: https://github.com/riscv/opensbi/issues/97
>> >
>> > V2:
>> >  - Squash patches to ensure biesctability
>> >
>> > Alistair Francis (2):
>> >   riscv: plic: Fix incorrect irq calculation
>> >   riscv: plic: Log guest errors
>> >
>> >  hw/riscv/sifive_plic.c      | 16 +++++++++++-----
>> >  hw/riscv/sifive_u.c         |  2 +-
>> >  include/hw/riscv/sifive_e.h |  2 +-
>> >  include/hw/riscv/sifive_u.h |  4 ++--
>> >  include/hw/riscv/virt.h     |  2 +-
>> >  5 files changed, 16 insertions(+), 10 deletions(-)
>> >
>> > --
>> > 2.21.0
>>
>> Thanks, I've got these on for-master.  I'll let them sit for a bit to see if
>> there are any other comments, but
>>
>> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>
> Ping! Just want to make sure these make it into 4.0

Thanks, this got lost in the shuffle.  I just forwarded along the PR.