Show patches with: Submitter = Alistair Francis       |   1798 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v1,17/36] target/riscv: Set VS bits in mideleg for Hyp extension Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,16/36] target/riscv: Add virtual register swapping function Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,15/36] target/riscv: Convert mstatus to pointers Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,14/36] target/riscv: Add Hypervisor virtual CSRs accesses Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,13/36] target/riscv: Add Hypervisor virtual CSRs accesses Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,12/36] target/riscv: Add Hypervisor CSR access functions Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,11/36] target/riscv: Dump Hypervisor registers if enabled Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,10/36] target/riscv: Print priv and virt in disas log Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,09/36] target/riscv: Fix CSR perm checking for HS mode Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,08/36] target/riscv: Add the force HS exception mode Add RISC-V Hypervisor Extension v0.5 - - - --- 2019-12-09 Alistair Francis New
[v1,07/36] target/riscv: Add the virtulisation mode Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,06/36] target/riscv: Rename the H irqs to VS irqs Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,05/36] target/riscv: Add support for the new execption numbers Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,04/36] target/riscv: Add the Hypervisor CSRs to CPUState Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,03/36] target/riscv: Add the Hypervisor extension Add RISC-V Hypervisor Extension v0.5 - 2 - --- 2019-12-09 Alistair Francis New
[v1,02/36] target/riscv: Don't set write permissions on dirty PTEs Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[v1,01/36] target/riscv: Convert MIP CSR to target_ulong Add RISC-V Hypervisor Extension v0.5 - 1 - --- 2019-12-09 Alistair Francis New
[for,4.2,v1,1/1] riscv/virt: Increase flash size [for,4.2,v1,1/1] riscv/virt: Increase flash size - 2 - --- 2019-11-07 Alistair Francis New
[v2,27/27] target/riscv: Allow enabling the Hypervisor extension Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-10-25 Alistair Francis New
[v2,26/27] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-10-25 Alistair Francis New
[v2,25/27] target/riscv: Add support for the 32-bit MSTATUSH CSR Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-10-25 Alistair Francis New
[v2,24/27] target/riscv: Implement second stage MMU Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-10-25 Alistair Francis New
[v2,23/27] target/riscv: Allow specifying MMU stage Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-10-25 Alistair Francis New
[v2,22/27] target/riscv: Respect MPRV and SPRV for floating point ops Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-10-25 Alistair Francis New
[v2,21/27] target/riscv: Mark both sstatus and vsstatus as dirty Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-10-25 Alistair Francis New
[v2,20/27] target/riscv: Disable guest FP support based on virtual status Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-10-25 Alistair Francis New
[v2,19/27] target/riscv: Add hfence instructions Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-10-25 Alistair Francis New
[v2,18/27] target/riscv: Add Hypervisor trap return support Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-10-25 Alistair Francis New
[v2,17/27] target/riscv: Add hypvervisor trap support Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-10-25 Alistair Francis New
[v2,16/27] riscv: plic: Always set sip.SEIP bit for HS Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-10-25 Alistair Francis New
[v2,15/27] target/riscv: Generate illegal instruction on WFI when V=1 Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-10-25 Alistair Francis New
[v2,14/27] target/ricsv: Flush the TLB on virtulisation mode changes Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-10-25 Alistair Francis New
[v2,13/27] target/riscv: Add support for virtual interrupt setting Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-10-25 Alistair Francis New
[v2,12/27] target/riscv: Add virtual register swapping function Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-10-25 Alistair Francis New
[v2,11/27] target/riscv: Convert mie and mstatus to pointers Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-10-25 Alistair Francis New
[v2,10/27] target/riscv: Add Hypervisor virtual CSRs accesses Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-10-25 Alistair Francis New
[v2,09/27] target/riscv: Add Hypervisor CSR access functions Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-10-25 Alistair Francis New
[v2,08/27] target/riscv: Dump Hypervisor registers if enabled Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-10-25 Alistair Francis New
[v2,07/27] target/riscv: Print priv and virt in disas log Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-10-25 Alistair Francis New
[v2,06/27] target/riscv: Add the Hypervisor CSRs to CPUState Add RISC-V Hypervisor Extension v0.4 - 2 - --- 2019-10-25 Alistair Francis New
[v2,05/27] target/riscv: Fix CSR perm checking for HS mode Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-10-25 Alistair Francis New
[v2,04/27] target/riscv: Add the force HS exception mode Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-10-25 Alistair Francis New
[v2,03/27] target/riscv: Add the virtulisation mode Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-10-25 Alistair Francis New
[v2,02/27] target/riscv: Add the Hypervisor extension Add RISC-V Hypervisor Extension v0.4 - 2 - --- 2019-10-25 Alistair Francis New
[v2,01/27] target/riscv: Don't set write permissions on dirty PTEs Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-10-25 Alistair Francis New
[v1,1/1] opensbi: Upgrade from v0.4 to v0.5 [v1,1/1] opensbi: Upgrade from v0.4 to v0.5 - - - --- 2019-10-25 Alistair Francis New
[v3,7/7] riscv/virt: Jump to pflash if specified RISC-V: Add more machine memory - 2 1 --- 2019-10-08 Alistair Francis New
[v3,6/7] riscv/virt: Add the PFlash CFI01 device RISC-V: Add more machine memory - 1 1 --- 2019-10-08 Alistair Francis New
[v3,5/7] riscv/virt: Manually define the machine RISC-V: Add more machine memory - 1 1 --- 2019-10-08 Alistair Francis New
[v3,4/7] riscv/sifive_u: Add the start-in-flash property RISC-V: Add more machine memory - 1 1 --- 2019-10-08 Alistair Francis New
[v3,3/7] riscv/sifive_u: Manually define the machine RISC-V: Add more machine memory - 1 1 --- 2019-10-08 Alistair Francis New
[v3,2/7] riscv/sifive_u: Add QSPI memory region RISC-V: Add more machine memory - 1 - --- 2019-10-08 Alistair Francis New
[v3,1/7] riscv/sifive_u: Add L2-LIM cache memory RISC-V: Add more machine memory - 1 - --- 2019-10-08 Alistair Francis New
[v1,1/1] target/riscv: Remove atomic accesses to MIP CSR [v1,1/1] target/riscv: Remove atomic accesses to MIP CSR 1 2 - --- 2019-10-08 Alistair Francis New
[v2,2/2] RISC-V: Implement cpu_do_transaction_failed RISC-V: Convert to do_transaction_failed hook - 2 - --- 2019-10-08 Alistair Francis New
[v2,1/2] RISC-V: Handle bus errors in the page table walker RISC-V: Convert to do_transaction_failed hook - 2 - --- 2019-10-08 Alistair Francis New
[v2,1/1] riscv/boot: Fix possible memory leak [v2,1/1] riscv/boot: Fix possible memory leak - 3 - --- 2019-10-03 Alistair Francis New
[v1,1/1] riscv/boot: Fix possible memory leak [v1,1/1] riscv/boot: Fix possible memory leak - 3 - --- 2019-10-02 Alistair Francis New
[v1,1/1] target/riscv: Print CPU and privledge in disas [v1,1/1] target/riscv: Print CPU and privledge in disas - 2 1 --- 2019-09-27 Alistair Francis New
[v2,7/7] riscv/virt: Jump to pflash if specified [v2,1/7] riscv/sifive_u: Add L2-LIM cache memory - 2 1 --- 2019-09-27 Alistair Francis New
[v2,6/7] riscv/virt: Add the PFlash CFI01 device [v2,1/7] riscv/sifive_u: Add L2-LIM cache memory - 1 1 --- 2019-09-27 Alistair Francis New
[v2,5/7] riscv/virt: Manually define the machine [v2,1/7] riscv/sifive_u: Add L2-LIM cache memory - 1 1 --- 2019-09-27 Alistair Francis New
[v2,4/7] riscv/sifive_u: Add the start-in-flash property [v2,1/7] riscv/sifive_u: Add L2-LIM cache memory - 1 - --- 2019-09-27 Alistair Francis New
[v2,3/7] riscv/sifive_u: Manually define the machine [v2,1/7] riscv/sifive_u: Add L2-LIM cache memory - 1 1 --- 2019-09-27 Alistair Francis New
[v2,2/7] riscv/sifive_u: Add QSPI memory region [v2,1/7] riscv/sifive_u: Add L2-LIM cache memory - 1 - --- 2019-09-27 Alistair Francis New
[v2,1/7] riscv/sifive_u: Add L2-LIM cache memory [v2,1/7] riscv/sifive_u: Add L2-LIM cache memory - 1 - --- 2019-09-27 Alistair Francis New
[v1,6/6] riscv/virt: Jump to pflash if specified RISC-V: Add more machine memory - 2 - --- 2019-09-19 Alistair Francis New
[v1,5/6] riscv/virt: Add the PFlash CFI01 device RISC-V: Add more machine memory - - - --- 2019-09-19 Alistair Francis New
[v1,4/6] riscv/sifive_u: Add the start-in-flash property RISC-V: Add more machine memory - - - --- 2019-09-19 Alistair Francis New
[v1,3/6] riscv/sifive_u: Manually define the machine RISC-V: Add more machine memory - - - --- 2019-09-19 Alistair Francis New
[v1,2/6] riscv/sifive_u: Add QSPI memory region RISC-V: Add more machine memory - - - --- 2019-09-19 Alistair Francis New
[v1,1/6] riscv/sifive_u: Add L2-LIM cache memory RISC-V: Add more machine memory - - - --- 2019-09-19 Alistair Francis New
[v1,2/2] RISC-V: Implement cpu_do_transaction_failed RISC-V: Convert to do_transaction_failed hook - 1 - --- 2019-09-17 Alistair Francis New
[v1,1/2] RISC-V: Handle bus errors in the page table walker RISC-V: Convert to do_transaction_failed hook - 1 - --- 2019-09-17 Alistair Francis New
[v1,28/28] target/riscv: Allow enabling the Hypervisor extension Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v1,27/28] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-08-23 Alistair Francis New
[v1,26/28] target/riscv: Add support for the 32-bit MSTATUSH CSR Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-08-23 Alistair Francis New
[v1,25/28] target/riscv: Call the second stage MMU in virtualisation mode Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v1,24/28] target/riscv: Implement second stage MMU Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v1,23/28] target/riscv: Allow specifying number of MMU stages Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-08-23 Alistair Francis New
[v1,22/28] target/riscv: Allow specifying MMU stage Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-08-23 Alistair Francis New
[v1,21/28] target/riscv: Respect MPRV and SPRV for floating point ops Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-08-23 Alistair Francis New
[v1,20/28] target/riscv: Mark both sstatus and vsstatus as dirty Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v1,19/28] target/riscv: Disable guest FP support based on virtual status Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v1,18/28] target/riscv: Add hfence instructions Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v1,17/28] target/riscv: Add Hypervisor trap return support Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v1,16/28] target/riscv: Add hypvervisor trap support Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v1,15/28] riscv: plic: Always set sip.SEIP bit for HS Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-08-23 Alistair Francis New
[v1,14/28] target/riscv: Generate illegal instruction on WFI when V=1 Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v1,13/28] target/ricsv: Flush the TLB on virtulisation mode changes Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v1,12/28] target/riscv: Add support for virtual interrupt setting Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v1,11/28] target/riscv: Add background register swapping function Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-08-23 Alistair Francis New
[v1,10/28] target/riscv: Convert mie and mstatus to pointers Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v1,09/28] target/riscv: Add Hypervisor virtual CSRs accesses Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v1,08/28] target/riscv: Add Hypervisor CSR access functions Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v1,07/28] target/riscv: Dump Hypervisor registers if enabled Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v1,06/28] target/riscv: Print priv and virt in disas log Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v1,05/28] target/riscv: Add the Hypervisor CSRs to CPUState Add RISC-V Hypervisor Extension v0.4 - 2 - --- 2019-08-23 Alistair Francis New
[v1,04/28] target/riscv: Fix CSR perm checking for HS mode Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-08-23 Alistair Francis New
[v1,03/28] target/riscv: Add the force HS exception mode Add RISC-V Hypervisor Extension v0.4 - - - --- 2019-08-23 Alistair Francis New
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