| Message ID | a24af06cea57073f4a75381755ab05e825679445.1569545046.git.alistair.francis@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/7] riscv/sifive_u: Add L2-LIM cache memory | expand |
On Fri, Sep 27, 2019 at 8:55 AM Alistair Francis <alistair.francis@wdc.com> wrote: > > Add a property that when set to true QEMU will jump from the ROM code to > the start of flash memory instead of DRAM which is the default > behaviour. > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++++++ > include/hw/riscv/sifive_u.h | 2 ++ > 2 files changed, 29 insertions(+) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index f5741e9a38..33b55d0d5b 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -373,6 +373,10 @@ static void riscv_sifive_u_init(MachineState *machine) > /* dtb: */ > }; > > + if (s->start_in_flash) { > + reset_vec[6] = memmap[SIFIVE_U_FLASH0].base; /* start: .dword FLASH0_BASE */ > + } Please change to use the way that patch "[v2,7/7] riscv/virt: Jump to pflash if specified" does for consistency, ie: if (s->start_in_flash) { start_addr = memmap[SIFIVE_U_FLASH0].base; /* start: .dword FLASH0_BASE */ } > + > /* copy in the reset vector in little_endian byte order */ > for (i = 0; i < sizeof(reset_vec) >> 2; i++) { > reset_vec[i] = cpu_to_le32(reset_vec[i]); > @@ -432,8 +436,31 @@ static void riscv_sifive_u_soc_init(Object *obj) > TYPE_CADENCE_GEM); > } > > +static bool virt_get_start_in_flash(Object *obj, Error **errp) sifive_u_get_start_in_flash() > +{ > + SiFiveUState *s = RISCV_U_MACHINE(obj); > + > + return s->start_in_flash; > +} > + > +static void virt_set_start_in_flash(Object *obj, bool value, Error **errp) sifive_u_set_start_in_flash() > +{ > + SiFiveUState *s = RISCV_U_MACHINE(obj); > + > + s->start_in_flash = value; > +} > + > static void riscv_sifive_u_machine_instance_init(Object *obj) > { > + SiFiveUState *s = RISCV_U_MACHINE(obj); > + > + s->start_in_flash = false; > + object_property_add_bool(obj, "start-in-flash", virt_get_start_in_flash, > + virt_set_start_in_flash, NULL); > + object_property_set_description(obj, "start-in-flash", > + "Set on to tell QEMU's ROM to jump to " \ > + "flash. Otherwise QEMU will jump to DRAM", > + NULL); > } > > static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h > index a921079fbe..2656b43c58 100644 > --- a/include/hw/riscv/sifive_u.h > +++ b/include/hw/riscv/sifive_u.h > @@ -57,6 +57,8 @@ typedef struct SiFiveUState { > > void *fdt; > int fdt_size; > + > + bool start_in_flash; > } SiFiveUState; > Regards, Bin
On Fri, Sep 27, 2019 at 12:57 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > On Fri, Sep 27, 2019 at 8:55 AM Alistair Francis > <alistair.francis@wdc.com> wrote: > > > > Add a property that when set to true QEMU will jump from the ROM code to > > the start of flash memory instead of DRAM which is the default > > behaviour. > > > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > > --- > > hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++++++ > > include/hw/riscv/sifive_u.h | 2 ++ > > 2 files changed, 29 insertions(+) > > > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > > index f5741e9a38..33b55d0d5b 100644 > > --- a/hw/riscv/sifive_u.c > > +++ b/hw/riscv/sifive_u.c > > @@ -373,6 +373,10 @@ static void riscv_sifive_u_init(MachineState *machine) > > /* dtb: */ > > }; > > > > + if (s->start_in_flash) { > > + reset_vec[6] = memmap[SIFIVE_U_FLASH0].base; /* start: .dword FLASH0_BASE */ > > + } > > Please change to use the way that patch "[v2,7/7] riscv/virt: Jump to > pflash if specified" does for consistency, ie: > > if (s->start_in_flash) { > start_addr = memmap[SIFIVE_U_FLASH0].base; /* start: .dword > FLASH0_BASE */ > } > > > + > > /* copy in the reset vector in little_endian byte order */ > > for (i = 0; i < sizeof(reset_vec) >> 2; i++) { > > reset_vec[i] = cpu_to_le32(reset_vec[i]); > > @@ -432,8 +436,31 @@ static void riscv_sifive_u_soc_init(Object *obj) > > TYPE_CADENCE_GEM); > > } > > > > +static bool virt_get_start_in_flash(Object *obj, Error **errp) > > sifive_u_get_start_in_flash() > > > +{ > > + SiFiveUState *s = RISCV_U_MACHINE(obj); > > + > > + return s->start_in_flash; > > +} > > + > > +static void virt_set_start_in_flash(Object *obj, bool value, Error **errp) > > sifive_u_set_start_in_flash() Yep, I have fixed all of these. Alistair > > > +{ > > + SiFiveUState *s = RISCV_U_MACHINE(obj); > > + > > + s->start_in_flash = value; > > +} > > + > > static void riscv_sifive_u_machine_instance_init(Object *obj) > > { > > + SiFiveUState *s = RISCV_U_MACHINE(obj); > > + > > + s->start_in_flash = false; > > + object_property_add_bool(obj, "start-in-flash", virt_get_start_in_flash, > > + virt_set_start_in_flash, NULL); > > + object_property_set_description(obj, "start-in-flash", > > + "Set on to tell QEMU's ROM to jump to " \ > > + "flash. Otherwise QEMU will jump to DRAM", > > + NULL); > > } > > > > static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) > > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h > > index a921079fbe..2656b43c58 100644 > > --- a/include/hw/riscv/sifive_u.h > > +++ b/include/hw/riscv/sifive_u.h > > @@ -57,6 +57,8 @@ typedef struct SiFiveUState { > > > > void *fdt; > > int fdt_size; > > + > > + bool start_in_flash; > > } SiFiveUState; > > > > Regards, > Bin
On Thu, 26 Sep 2019 17:44:28 PDT (-0700), Alistair Francis wrote: > Add a property that when set to true QEMU will jump from the ROM code to > the start of flash memory instead of DRAM which is the default > behaviour. > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++++++ > include/hw/riscv/sifive_u.h | 2 ++ > 2 files changed, 29 insertions(+) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index f5741e9a38..33b55d0d5b 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -373,6 +373,10 @@ static void riscv_sifive_u_init(MachineState *machine) > /* dtb: */ > }; > > + if (s->start_in_flash) { > + reset_vec[6] = memmap[SIFIVE_U_FLASH0].base; /* start: .dword FLASH0_BASE */ > + } > + > /* copy in the reset vector in little_endian byte order */ > for (i = 0; i < sizeof(reset_vec) >> 2; i++) { > reset_vec[i] = cpu_to_le32(reset_vec[i]); > @@ -432,8 +436,31 @@ static void riscv_sifive_u_soc_init(Object *obj) > TYPE_CADENCE_GEM); > } > > +static bool virt_get_start_in_flash(Object *obj, Error **errp) > +{ > + SiFiveUState *s = RISCV_U_MACHINE(obj); > + > + return s->start_in_flash; > +} > + > +static void virt_set_start_in_flash(Object *obj, bool value, Error **errp) > +{ > + SiFiveUState *s = RISCV_U_MACHINE(obj); > + > + s->start_in_flash = value; > +} > + > static void riscv_sifive_u_machine_instance_init(Object *obj) > { > + SiFiveUState *s = RISCV_U_MACHINE(obj); > + > + s->start_in_flash = false; > + object_property_add_bool(obj, "start-in-flash", virt_get_start_in_flash, > + virt_set_start_in_flash, NULL); > + object_property_set_description(obj, "start-in-flash", > + "Set on to tell QEMU's ROM to jump to " \ > + "flash. Otherwise QEMU will jump to DRAM", > + NULL); > } > > static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h > index a921079fbe..2656b43c58 100644 > --- a/include/hw/riscv/sifive_u.h > +++ b/include/hw/riscv/sifive_u.h > @@ -57,6 +57,8 @@ typedef struct SiFiveUState { > > void *fdt; > int fdt_size; > + > + bool start_in_flash; > } SiFiveUState; > > enum { Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
On Mon, 30 Sep 2019 11:04:45 PDT (-0700), alistair23@gmail.com wrote: > On Fri, Sep 27, 2019 at 12:57 AM Bin Meng <bmeng.cn@gmail.com> wrote: >> >> On Fri, Sep 27, 2019 at 8:55 AM Alistair Francis >> <alistair.francis@wdc.com> wrote: >> > >> > Add a property that when set to true QEMU will jump from the ROM code to >> > the start of flash memory instead of DRAM which is the default >> > behaviour. >> > >> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> >> > --- >> > hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++++++ >> > include/hw/riscv/sifive_u.h | 2 ++ >> > 2 files changed, 29 insertions(+) >> > >> > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c >> > index f5741e9a38..33b55d0d5b 100644 >> > --- a/hw/riscv/sifive_u.c >> > +++ b/hw/riscv/sifive_u.c >> > @@ -373,6 +373,10 @@ static void riscv_sifive_u_init(MachineState *machine) >> > /* dtb: */ >> > }; >> > >> > + if (s->start_in_flash) { >> > + reset_vec[6] = memmap[SIFIVE_U_FLASH0].base; /* start: .dword FLASH0_BASE */ >> > + } >> >> Please change to use the way that patch "[v2,7/7] riscv/virt: Jump to >> pflash if specified" does for consistency, ie: >> >> if (s->start_in_flash) { >> start_addr = memmap[SIFIVE_U_FLASH0].base; /* start: .dword >> FLASH0_BASE */ >> } >> >> > + >> > /* copy in the reset vector in little_endian byte order */ >> > for (i = 0; i < sizeof(reset_vec) >> 2; i++) { >> > reset_vec[i] = cpu_to_le32(reset_vec[i]); >> > @@ -432,8 +436,31 @@ static void riscv_sifive_u_soc_init(Object *obj) >> > TYPE_CADENCE_GEM); >> > } >> > >> > +static bool virt_get_start_in_flash(Object *obj, Error **errp) >> >> sifive_u_get_start_in_flash() >> >> > +{ >> > + SiFiveUState *s = RISCV_U_MACHINE(obj); >> > + >> > + return s->start_in_flash; >> > +} >> > + >> > +static void virt_set_start_in_flash(Object *obj, bool value, Error **errp) >> >> sifive_u_set_start_in_flash() > > Yep, I have fixed all of these. Did I miss the v3? > > Alistair > >> >> > +{ >> > + SiFiveUState *s = RISCV_U_MACHINE(obj); >> > + >> > + s->start_in_flash = value; >> > +} >> > + >> > static void riscv_sifive_u_machine_instance_init(Object *obj) >> > { >> > + SiFiveUState *s = RISCV_U_MACHINE(obj); >> > + >> > + s->start_in_flash = false; >> > + object_property_add_bool(obj, "start-in-flash", virt_get_start_in_flash, >> > + virt_set_start_in_flash, NULL); >> > + object_property_set_description(obj, "start-in-flash", >> > + "Set on to tell QEMU's ROM to jump to " \ >> > + "flash. Otherwise QEMU will jump to DRAM", >> > + NULL); >> > } >> > >> > static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) >> > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h >> > index a921079fbe..2656b43c58 100644 >> > --- a/include/hw/riscv/sifive_u.h >> > +++ b/include/hw/riscv/sifive_u.h >> > @@ -57,6 +57,8 @@ typedef struct SiFiveUState { >> > >> > void *fdt; >> > int fdt_size; >> > + >> > + bool start_in_flash; >> > } SiFiveUState; >> > >> >> Regards, >> Bin
On Tue, Oct 8, 2019 at 1:12 PM Palmer Dabbelt <palmer@sifive.com> wrote: > > On Mon, 30 Sep 2019 11:04:45 PDT (-0700), alistair23@gmail.com wrote: > > On Fri, Sep 27, 2019 at 12:57 AM Bin Meng <bmeng.cn@gmail.com> wrote: > >> > >> On Fri, Sep 27, 2019 at 8:55 AM Alistair Francis > >> <alistair.francis@wdc.com> wrote: > >> > > >> > Add a property that when set to true QEMU will jump from the ROM code to > >> > the start of flash memory instead of DRAM which is the default > >> > behaviour. > >> > > >> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > >> > --- > >> > hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++++++ > >> > include/hw/riscv/sifive_u.h | 2 ++ > >> > 2 files changed, 29 insertions(+) > >> > > >> > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > >> > index f5741e9a38..33b55d0d5b 100644 > >> > --- a/hw/riscv/sifive_u.c > >> > +++ b/hw/riscv/sifive_u.c > >> > @@ -373,6 +373,10 @@ static void riscv_sifive_u_init(MachineState *machine) > >> > /* dtb: */ > >> > }; > >> > > >> > + if (s->start_in_flash) { > >> > + reset_vec[6] = memmap[SIFIVE_U_FLASH0].base; /* start: .dword FLASH0_BASE */ > >> > + } > >> > >> Please change to use the way that patch "[v2,7/7] riscv/virt: Jump to > >> pflash if specified" does for consistency, ie: > >> > >> if (s->start_in_flash) { > >> start_addr = memmap[SIFIVE_U_FLASH0].base; /* start: .dword > >> FLASH0_BASE */ > >> } > >> > >> > + > >> > /* copy in the reset vector in little_endian byte order */ > >> > for (i = 0; i < sizeof(reset_vec) >> 2; i++) { > >> > reset_vec[i] = cpu_to_le32(reset_vec[i]); > >> > @@ -432,8 +436,31 @@ static void riscv_sifive_u_soc_init(Object *obj) > >> > TYPE_CADENCE_GEM); > >> > } > >> > > >> > +static bool virt_get_start_in_flash(Object *obj, Error **errp) > >> > >> sifive_u_get_start_in_flash() > >> > >> > +{ > >> > + SiFiveUState *s = RISCV_U_MACHINE(obj); > >> > + > >> > + return s->start_in_flash; > >> > +} > >> > + > >> > +static void virt_set_start_in_flash(Object *obj, bool value, Error **errp) > >> > >> sifive_u_set_start_in_flash() > > > > Yep, I have fixed all of these. > > Did I miss the v3? Nope, I'll send it today. Alistair > > > > > Alistair > > > >> > >> > +{ > >> > + SiFiveUState *s = RISCV_U_MACHINE(obj); > >> > + > >> > + s->start_in_flash = value; > >> > +} > >> > + > >> > static void riscv_sifive_u_machine_instance_init(Object *obj) > >> > { > >> > + SiFiveUState *s = RISCV_U_MACHINE(obj); > >> > + > >> > + s->start_in_flash = false; > >> > + object_property_add_bool(obj, "start-in-flash", virt_get_start_in_flash, > >> > + virt_set_start_in_flash, NULL); > >> > + object_property_set_description(obj, "start-in-flash", > >> > + "Set on to tell QEMU's ROM to jump to " \ > >> > + "flash. Otherwise QEMU will jump to DRAM", > >> > + NULL); > >> > } > >> > > >> > static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) > >> > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h > >> > index a921079fbe..2656b43c58 100644 > >> > --- a/include/hw/riscv/sifive_u.h > >> > +++ b/include/hw/riscv/sifive_u.h > >> > @@ -57,6 +57,8 @@ typedef struct SiFiveUState { > >> > > >> > void *fdt; > >> > int fdt_size; > >> > + > >> > + bool start_in_flash; > >> > } SiFiveUState; > >> > > >> > >> Regards, > >> Bin
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index f5741e9a38..33b55d0d5b 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -373,6 +373,10 @@ static void riscv_sifive_u_init(MachineState *machine) /* dtb: */ }; + if (s->start_in_flash) { + reset_vec[6] = memmap[SIFIVE_U_FLASH0].base; /* start: .dword FLASH0_BASE */ + } + /* copy in the reset vector in little_endian byte order */ for (i = 0; i < sizeof(reset_vec) >> 2; i++) { reset_vec[i] = cpu_to_le32(reset_vec[i]); @@ -432,8 +436,31 @@ static void riscv_sifive_u_soc_init(Object *obj) TYPE_CADENCE_GEM); } +static bool virt_get_start_in_flash(Object *obj, Error **errp) +{ + SiFiveUState *s = RISCV_U_MACHINE(obj); + + return s->start_in_flash; +} + +static void virt_set_start_in_flash(Object *obj, bool value, Error **errp) +{ + SiFiveUState *s = RISCV_U_MACHINE(obj); + + s->start_in_flash = value; +} + static void riscv_sifive_u_machine_instance_init(Object *obj) { + SiFiveUState *s = RISCV_U_MACHINE(obj); + + s->start_in_flash = false; + object_property_add_bool(obj, "start-in-flash", virt_get_start_in_flash, + virt_set_start_in_flash, NULL); + object_property_set_description(obj, "start-in-flash", + "Set on to tell QEMU's ROM to jump to " \ + "flash. Otherwise QEMU will jump to DRAM", + NULL); } static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index a921079fbe..2656b43c58 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -57,6 +57,8 @@ typedef struct SiFiveUState { void *fdt; int fdt_size; + + bool start_in_flash; } SiFiveUState; enum {
Add a property that when set to true QEMU will jump from the ROM code to the start of flash memory instead of DRAM which is the default behaviour. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++++++ include/hw/riscv/sifive_u.h | 2 ++ 2 files changed, 29 insertions(+)