Show patches with: Submitter = Alistair Francis       |   1798 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v1,02/28] target/riscv: Add the virtulisation mode Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v1,01/28] target/riscv: Add the Hypervisor extension Add RISC-V Hypervisor Extension v0.4 - 1 - --- 2019-08-23 Alistair Francis New
[v4,7/7] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point RISC-V: Hypervisor prep work part 2 - 1 - --- 2019-08-23 Alistair Francis New
[v4,6/7] target/riscv: Fix mstatus dirty mask RISC-V: Hypervisor prep work part 2 - 1 - --- 2019-08-23 Alistair Francis New
[v4,5/7] target/riscv: Use both register name and ABI name RISC-V: Hypervisor prep work part 2 - 1 - --- 2019-08-23 Alistair Francis New
[v4,4/7] target/riscv: Update the Hypervisor CSRs to v0.4 RISC-V: Hypervisor prep work part 2 - 2 - --- 2019-08-23 Alistair Francis New
[v4,3/7] target/riscv: Create function to test if FP is enabled RISC-V: Hypervisor prep work part 2 - 4 - --- 2019-08-23 Alistair Francis New
[v4,2/7] riscv: plic: Remove unused interrupt functions RISC-V: Hypervisor prep work part 2 - 4 - --- 2019-08-23 Alistair Francis New
[v4,1/7] target/riscv: Don't set write permissions on dirty PTEs RISC-V: Hypervisor prep work part 2 - 1 - --- 2019-08-23 Alistair Francis New
[v3,7/7] target/riscv: Convert mip to target_ulong RISC-V: Hypervisor prep work part 2 - 1 - --- 2019-08-15 Alistair Francis New
[v3,6/7] target/riscv: Fix mstatus dirty mask RISC-V: Hypervisor prep work part 2 - 1 - --- 2019-08-15 Alistair Francis New
[v3,5/7] target/riscv: Use both register name and ABI name RISC-V: Hypervisor prep work part 2 - 1 - --- 2019-08-15 Alistair Francis New
[v3,4/7] target/riscv: Update the Hypervisor CSRs to v0.4 RISC-V: Hypervisor prep work part 2 - 2 - --- 2019-08-15 Alistair Francis New
[v3,3/7] target/riscv: Create function to test if FP is enabled RISC-V: Hypervisor prep work part 2 - 4 - --- 2019-08-15 Alistair Francis New
[v3,2/7] riscv: plic: Remove unused interrupt functions RISC-V: Hypervisor prep work part 2 - 4 - --- 2019-08-15 Alistair Francis New
[v3,1/7] target/riscv: Don't set write permissions on dirty PTEs RISC-V: Hypervisor prep work part 2 - 1 - --- 2019-08-15 Alistair Francis New
[PATCH-4.2,v2,5/5] target/riscv: Fix Floating Point register names RISC-V: Hypervisor prep work part 2 - - - --- 2019-07-30 Alistair Francis New
[PATCH-4.2,v2,4/5] target/riscv: Update the Hypervisor CSRs to v0.4 RISC-V: Hypervisor prep work part 2 - - - --- 2019-07-30 Alistair Francis New
[PATCH-4.2,v2,3/5] target/riscv: Create function to test if FP is enabled RISC-V: Hypervisor prep work part 2 - 2 - --- 2019-07-30 Alistair Francis New
[PATCH-4.2,v2,2/5] riscv: plic: Remove unused interrupt functions RISC-V: Hypervisor prep work part 2 - 3 - --- 2019-07-30 Alistair Francis New
[PATCH-4.2,v2,1/5] target/riscv: Don't set write permissions on dirty PTEs RISC-V: Hypervisor prep work part 2 - - - --- 2019-07-30 Alistair Francis New
[PATCH-4.2,v1,6/6] target/riscv: Fix Floating Point register names RISC-V: Hypervisor prep work part 2 - - - --- 2019-07-25 Alistair Francis New
[PATCH-4.2,v1,5/6] target/riscv: Update the Hypervisor CSRs to v0.4 RISC-V: Hypervisor prep work part 2 - - - --- 2019-07-25 Alistair Francis New
[PATCH-4.2,v1,4/6] target/riscv: Create function to test if FP is enabled RISC-V: Hypervisor prep work part 2 - 2 - --- 2019-07-25 Alistair Francis New
[PATCH-4.2,v1,3/6] riscv: plic: Remove unused interrupt functions RISC-V: Hypervisor prep work part 2 - 3 - --- 2019-07-25 Alistair Francis New
[PATCH-4.2,v1,2/6] target/riscv: Remove strict perm checking for CSR R/W RISC-V: Hypervisor prep work part 2 - - - --- 2019-07-25 Alistair Francis New
[PATCH-4.2,v1,1/6] target/riscv: Don't set write permissions on dirty PTEs RISC-V: Hypervisor prep work part 2 - - - --- 2019-07-25 Alistair Francis New
[v2,1/1] riscv/boot: Fixup the RISC-V firmware warning [v2,1/1] riscv/boot: Fixup the RISC-V firmware warning - 1 - --- 2019-07-22 Alistair Francis New
[v1,1/1] riscv/boot: Fixup the RISC-V firmware warning [v1,1/1] riscv/boot: Fixup the RISC-V firmware warning - 1 - --- 2019-07-19 Alistair Francis New
[v3,2/2] hw/riscv: Load OpenSBI as the default firmware RISC-V: Add default OpenSBI ROM - 2 2 --- 2019-07-16 Alistair Francis New
[v3,1/2] roms: Add OpenSBI version 0.4 RISC-V: Add default OpenSBI ROM - 2 1 --- 2019-07-16 Alistair Francis New
[v2,2/2] hw/riscv: Load OpenSBI as the default firmware RISC-V: Add default OpenSBI ROM - 2 2 --- 2019-07-11 Alistair Francis New
[v2,1/2] roms: Add OpenSBI version 0.4 RISC-V: Add default OpenSBI ROM - 2 1 --- 2019-07-11 Alistair Francis New
[v1,2/2] hw/riscv: Load OpenSBI as the default firmware RISC-V: Add default OpenSBI ROM - 1 1 --- 2019-07-08 Alistair Francis New
[v1,1/2] roms: Add OpenSBI version 0.4 RISC-V: Add default OpenSBI ROM - 1 - --- 2019-07-08 Alistair Francis New
fixup! roms: Add OpenSBI version 0.3 fixup! roms: Add OpenSBI version 0.3 - - - --- 2019-06-28 Alistair Francis New
[v1,1/1] hw/scsi: Report errors and sense to guests through scsi-block [v1,1/1] hw/scsi: Report errors and sense to guests through scsi-block - - - --- 2019-06-26 Alistair Francis New
[v2,4/4] target/riscv: Implement riscv_cpu_unassigned_access Miscellaneous patches from the RISC-V fork - - - --- 2019-06-24 Alistair Francis New
[v2,3/4] disas/riscv: Fix `rdinstreth` constraint Miscellaneous patches from the RISC-V fork - - - --- 2019-06-24 Alistair Francis New
[v2,2/4] disas/riscv: Disassemble reserved compressed encodings as illegal Miscellaneous patches from the RISC-V fork - - - --- 2019-06-24 Alistair Francis New
[v2,1/4] target/riscv: Fix PMP range boundary address bug Miscellaneous patches from the RISC-V fork - 2 - --- 2019-06-24 Alistair Francis New
[v1,5/5] hw/riscv: Load OpenSBI as the default firmware RISC-V: Add firmware loading support and default - 1 1 --- 2019-06-24 Alistair Francis New
[v1,4/5] roms: Add OpenSBI version 0.3 RISC-V: Add firmware loading support and default - 1 1 --- 2019-06-24 Alistair Francis New
[v1,3/5] hw/riscv: Extend the kernel loading support RISC-V: Add firmware loading support and default - 1 1 --- 2019-06-24 Alistair Francis New
[v1,2/5] hw/riscv: Add support for loading a firmware RISC-V: Add firmware loading support and default - 1 1 --- 2019-06-24 Alistair Francis New
[v1,1/5] hw/riscv: Split out the boot functions RISC-V: Add firmware loading support and default - 1 1 --- 2019-06-24 Alistair Francis New
[v1,1/1] tcg/riscv: Fix RISC-VH host build failure [v1,1/1] tcg/riscv: Fix RISC-VH host build failure - - - --- 2019-06-20 Alistair Francis New
[RFC,v1,5/5] hw/riscv: Load OpenSBI as the default firmware RISC-V: Add firmware loading support and default - - - --- 2019-06-19 Alistair Francis New
[RFC,v1,4/5] roms: Add OpenSBI version 0.3 RISC-V: Add firmware loading support and default - - - --- 2019-06-19 Alistair Francis New
[RFC,v1,3/5] hw/riscv: Extend the kernel loading support RISC-V: Add firmware loading support and default - - - --- 2019-06-19 Alistair Francis New
[RFC,v1,2/5] hw/riscv: Add support for loading a firmware RISC-V: Add firmware loading support and default - - - --- 2019-06-19 Alistair Francis New
[RFC,v1,1/5] hw/riscv: Split out the boot functions RISC-V: Add firmware loading support and default - 1 1 --- 2019-06-19 Alistair Francis New
[v1,9/9] target/riscv: Add Zifencei and Zicsr as command line options Update the RISC-V specification versions - - - --- 2019-06-18 Alistair Francis New
[v1,8/9] target/riscv: Add support for disabling/enabling Counters Update the RISC-V specification versions - - - --- 2019-06-18 Alistair Francis New
[v1,7/9] target/riscv: Remove user version information Update the RISC-V specification versions - - - --- 2019-06-18 Alistair Francis New
[v1,6/9] target/riscv: Require either I or E base extension Update the RISC-V specification versions - - - --- 2019-06-18 Alistair Francis New
[v1,5/9] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 Update the RISC-V specification versions - - - --- 2019-06-18 Alistair Francis New
[v1,4/9] target/riscv: Set privledge spec 1.11.0 as default Update the RISC-V specification versions - - - --- 2019-06-18 Alistair Francis New
[v1,3/9] target/riscv: Comment in the mcountinhibit CSR Update the RISC-V specification versions - - - --- 2019-06-18 Alistair Francis New
[v1,2/9] target/riscv: Add the privledge spec version 1.11.0 Update the RISC-V specification versions - - - --- 2019-06-18 Alistair Francis New
[v1,1/9] target/riscv: Restructure deprecatd CPUs Update the RISC-V specification versions - - - --- 2019-06-18 Alistair Francis New
[v1,27/27] target/riscv: Allow enabling the Hypervisor extension Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,26/27] target/riscv: Call the second stage MMU in virtualisation mode Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,25/27] target/riscv: Implement second stage MMU Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,24/27] target/riscv: Allow specifying number of MMU stages Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,23/27] target/riscv: Allow specifying MMU stage Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,22/27] target/riscv: Respect MPRV and SPRV for floating point ops Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,21/27] target/riscv: Mark both sstatus and bsstatus as dirty Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,20/27] target/riscv: Disable guest FP support based on backgrond status Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,19/27] target/riscv: Add hfence instructions Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,18/27] target/riscv: Add Hypervisor trap return support Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,17/27] target/riscv: Add hypvervisor trap support Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,16/27] riscv: plic: Always set sip.SEIP bit for HS Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,15/27] riscv: plic: Remove unused interrupt functions Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,14/27] target/riscv: Generate illegal instruction on WFI when V=1 Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,13/27] target/ricsv: Flush the TLB on virtulisation mode changes Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,12/27] target/riscv: Add background register swapping function Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,11/27] target/riscv: Add background CSRs accesses Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,10/27] target/riscv: Add Hypervisor CSR access functions Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,09/27] target/riscv: Add support for background interrupt setting Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,08/27] target/riscv: Create function to test if FP is enabled Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,07/27] target/riscv: Remove strict perm checking for CSR R/W Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,06/27] target/riscv: Dump Hypervisor registers if enabled Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,05/27] target/riscv: Add the Hypervisor CSRs to CPUState Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,04/27] target/riscv: Add the force HS exception mode Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,03/27] target/riscv: Add the virtulisation mode Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,02/27] target/riscv: Add the Hypervisor extension Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[v1,01/27] target/riscv: Don't set write permissions on dirty PTEs Add RISC-V Hypervisor Extension - - - --- 2019-06-07 Alistair Francis New
[RFC,v1,23/23] target/riscv: Allow enabling the Hypervisor extension Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,22/23] target/riscv: Call the second stage MMU in virtualisation mode Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,21/23] target/riscv: Implement second stage MMU Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,20/23] target/riscv: Allow specifying number of MMU stages Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,19/23] target/riscv: Allow specifying MMU stage Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,18/23] target/riscv: Add hfence instructions Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,17/23] target/riscv: Add Hypervisor trap return support Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,16/23] target/riscv: Add hypvervisor trap support Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,15/23] riscv: plic: Always set sip.SEIP bit for HS Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,14/23] riscv: plic: Remove unused interrupt functions Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,13/23] target/riscv: Generate illegal instruction on WFI when V=1 Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
[RFC,v1,12/23] target/ricsv: Flush the TLB on virtulisation mode changes Add RISC-V Hypervisor Extension - - - --- 2019-05-24 Alistair Francis New
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