Show patches with: Submitter = Alistair Francis       |    State = Action Required       |   1798 patches
« 1 2 3 4 … 17 18 »
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v3,3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer OpenTitan: Add support for the RISC-V timer - 1 - --- 2021-06-18 Alistair Francis New
[v3,2/3] hw/timer: Initial commit of Ibex Timer OpenTitan: Add support for the RISC-V timer - 1 - --- 2021-06-18 Alistair Francis New
[v3,1/3] hw/char/ibex_uart: Make the register layout private OpenTitan: Add support for the RISC-V timer - 1 - --- 2021-06-18 Alistair Francis New
[v2,3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer hw/riscv: OpenTitan: Add support for the RISC-V timer - 1 - --- 2021-06-08 Alistair Francis New
[v2,2/3] hw/timer: Initial commit of Ibex Timer hw/riscv: OpenTitan: Add support for the RISC-V timer - - - --- 2021-06-08 Alistair Francis New
[v2,1/3] hw/char/ibex_uart: Make the register layout private hw/riscv: OpenTitan: Add support for the RISC-V timer - 1 - --- 2021-06-08 Alistair Francis New
[PULL,32/32] target/riscv: rvb: add b-ext version cpu option [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 1 - --- 2021-06-08 Alistair Francis New
[PULL,31/32] target/riscv: rvb: support and turn on B-extension from command line [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 2 - --- 2021-06-08 Alistair Francis New
[PULL,30/32] target/riscv: rvb: add/shift with prefix zero-extend [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 1 - --- 2021-06-08 Alistair Francis New
[PULL,29/32] target/riscv: rvb: address calculation [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 1 - --- 2021-06-08 Alistair Francis New
[PULL,28/32] target/riscv: rvb: generalized or-combine [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 1 - --- 2021-06-08 Alistair Francis New
[PULL,27/32] target/riscv: rvb: generalized reverse [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 1 - --- 2021-06-08 Alistair Francis New
[PULL,26/32] target/riscv: rvb: rotate (left/right) [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 2 - --- 2021-06-08 Alistair Francis New
[PULL,25/32] target/riscv: rvb: shift ones [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 2 - --- 2021-06-08 Alistair Francis New
[PULL,24/32] target/riscv: rvb: single-bit instructions [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 2 - --- 2021-06-08 Alistair Francis New
[PULL,23/32] target/riscv: add gen_shifti() and gen_shiftiw() helper functions [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 2 - --- 2021-06-08 Alistair Francis New
[PULL,22/32] target/riscv: rvb: sign-extend instructions [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 2 - --- 2021-06-08 Alistair Francis New
[PULL,21/32] target/riscv: rvb: min/max instructions [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 2 - --- 2021-06-08 Alistair Francis New
[PULL,20/32] target/riscv: rvb: pack two words into one register [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 2 - --- 2021-06-08 Alistair Francis New
[PULL,19/32] target/riscv: rvb: logic-with-negate [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 2 - --- 2021-06-08 Alistair Francis New
[PULL,18/32] target/riscv: rvb: count bits set [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 2 - --- 2021-06-08 Alistair Francis New
[PULL,17/32] target/riscv: rvb: count leading/trailing zeros [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 2 - --- 2021-06-08 Alistair Francis New
[PULL,16/32] target/riscv: reformat @sh format encoding for B-extension [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 2 - --- 2021-06-08 Alistair Francis New
[PULL,15/32] target/riscv: Pass the same value to oprsz and maxsz. [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 1 - --- 2021-06-08 Alistair Francis New
[PULL,14/32] target/riscv/pmp: Add assert for ePMP operations [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 2 - --- 2021-06-08 Alistair Francis New
[PULL,13/32] target/riscv: Dump CSR mscratch/sscratch/satp [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 2 - --- 2021-06-08 Alistair Francis New
[PULL,12/32] target/riscv: Remove unnecessary riscv_*_names[] declaration [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 2 - --- 2021-06-08 Alistair Francis New
[PULL,11/32] target/riscv: Do not include 'pmp.h' in user emulation [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 2 - --- 2021-06-08 Alistair Francis New
[PULL,10/32] docs/system: Move the RISC-V -bios information to removed [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 1 - --- 2021-06-08 Alistair Francis New
[PULL,09/32] target/riscv: fix wfi exception behavior [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 1 - --- 2021-06-08 Alistair Francis New
[PULL,08/32] hw/riscv: microchip_pfsoc: Support direct kernel boot [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 1 - --- 2021-06-08 Alistair Francis New
[PULL,07/32] hw/riscv: Use macros for BIOS image names [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 1 - --- 2021-06-08 Alistair Francis New
[PULL,06/32] docs/system/riscv: sifive_u: Document '-dtb' usage [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 1 - --- 2021-06-08 Alistair Francis New
[PULL,05/32] docs/system/riscv: Correct the indentation level of supported devices [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 1 - --- 2021-06-08 Alistair Francis New
[PULL,04/32] hw/riscv: Support the official PLIC DT bindings [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 1 - --- 2021-06-08 Alistair Francis New
[PULL,03/32] hw/riscv: Support the official CLINT DT bindings [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 1 - --- 2021-06-08 Alistair Francis New
[PULL,02/32] hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 1 - --- 2021-06-08 Alistair Francis New
[PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - 1 - --- 2021-06-08 Alistair Francis New
[PULL,00/32] riscv-to-apply queue - - - --- 2021-06-08 Alistair Francis New
[v1,3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer hw/riscv: OpenTitan: Add support for the RISC-V timer - - - --- 2021-05-31 Alistair Francis New
[v1,2/3] hw/timer: Initial commit of Ibex Timer hw/riscv: OpenTitan: Add support for the RISC-V timer - - - --- 2021-05-31 Alistair Francis New
[v1,1/3] hw/char/ibex_uart: Make the register layout private hw/riscv: OpenTitan: Add support for the RISC-V timer - 1 - --- 2021-05-31 Alistair Francis New
[v1,1/1] target/riscv: Use target_ulong for the DisasContext misa [v1,1/1] target/riscv: Use target_ulong for the DisasContext misa - 1 - --- 2021-05-31 Alistair Francis New
[v1,1/1] target/riscv/pmp: Add assert for ePMP operations [v1,1/1] target/riscv/pmp: Add assert for ePMP operations - 2 - --- 2021-05-20 Alistair Francis New
[PULL,v3,42/42] target/riscv: Fix the RV64H decode comment [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,41/42] target/riscv: Consolidate RV32/64 16-bit instructions [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,40/42] target/riscv: Consolidate RV32/64 32-bit instructions [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,39/42] target/riscv: Remove an unused CASE_OP_32_64 macro [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-11 Alistair Francis New
[PULL,v3,38/42] target/riscv: Remove the unused HSTATUS_WPRI macro [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-11 Alistair Francis New
[PULL,v3,37/42] target/riscv: Remove the hardcoded SATP_MODE macro [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,35/42] target/riscv: Remove the hardcoded HGATP_MODE macro [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-11 Alistair Francis New
[PULL,v3,34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-11 Alistair Francis New
[PULL,v3,33/42] target/riscv: Remove the hardcoded RVXLEN macro [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-11 Alistair Francis New
[PULL,v3,32/42] target/riscv: fix a typo with interrupt names [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,30/42] hw/riscv: Fix OT IBEX reset vector [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,29/42] target/riscv: fix exception index on instruction access fault [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,28/42] target/riscv: fix vrgather macro index variable type bug [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,27/42] target/riscv: Add ePMP support for the Ibex CPU [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,26/42] target/riscv/pmp: Remove outdated comment [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,25/42] target/riscv: Add a config option for ePMP [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-11 Alistair Francis New
[PULL,v3,24/42] target/riscv: Implementation of enhanced PMP (ePMP) [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,23/42] target/riscv: Add ePMP CSR access functions [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-11 Alistair Francis New
[PULL,v3,22/42] target/riscv: Add the ePMP feature [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,21/42] target/riscv: Define ePMP mseccfg [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 3 - --- 2021-05-11 Alistair Francis New
[PULL,v3,20/42] target/riscv: Fix the PMP is locked check when using TOR [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,19/42] docs: Add documentation for shakti_c machine [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,18/42] target/riscv: Fixup saturate subtract function [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-11 Alistair Francis New
[PULL,v3,17/42] riscv: don't look at SUM when accessing memory from a debugger context [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,15/42] hw/opentitan: Update the interrupt layout [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,14/42] MAINTAINERS: Update the RISC-V CPU Maintainers [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code 2 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,13/42] target/riscv: Use RISCVException enum for CSR access [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-11 Alistair Francis New
[PULL,v3,12/42] target/riscv: Use the RISCVException enum for CSR operations [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-11 Alistair Francis New
[PULL,v3,11/42] target/riscv: Fix 32-bit HS mode access permissions [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-11 Alistair Francis New
[PULL,v3,10/42] target/riscv: Use the RISCVException enum for CSR predicates [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-11 Alistair Francis New
[PULL,v3,09/42] target/riscv: Convert the RISC-V exceptions to an enum [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-11 Alistair Francis New
[PULL,v3,08/42] hw/riscv: Connect Shakti UART to Shakti platform [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,07/42] hw/char: Add Shakti UART emulation [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,06/42] riscv: Add initial support for Shakti C machine [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,05/42] target/riscv: Add Shakti C class CPU [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-11 Alistair Francis New
[PULL,v3,03/42] target/riscv: Align the data type of reset vector address [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-11 Alistair Francis New
[PULL,v3,02/42] docs/system/generic-loader.rst: Fix style [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code [PULL,v3,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-11 Alistair Francis New
[PULL,v3,00/42] riscv-to-apply queue - - - --- 2021-05-11 Alistair Francis New
[PULL,v2,42/42] target/riscv: Fix the RV64H decode comment [PULL,v2,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-05 Alistair Francis New
[PULL,v2,41/42] target/riscv: Consolidate RV32/64 16-bit instructions [PULL,v2,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-05 Alistair Francis New
[PULL,v2,40/42] target/riscv: Consolidate RV32/64 32-bit instructions [PULL,v2,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-05 Alistair Francis New
[PULL,v2,39/42] target/riscv: Remove an unused CASE_OP_32_64 macro [PULL,v2,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-05 Alistair Francis New
[PULL,v2,38/42] target/riscv: Remove the unused HSTATUS_WPRI macro [PULL,v2,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-05 Alistair Francis New
[PULL,v2,37/42] target/riscv: Remove the hardcoded SATP_MODE macro [PULL,v2,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-05 Alistair Francis New
[PULL,v2,36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro [PULL,v2,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-05 Alistair Francis New
[PULL,v2,35/42] target/riscv: Remove the hardcoded HGATP_MODE macro [PULL,v2,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-05 Alistair Francis New
[PULL,v2,34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro [PULL,v2,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-05 Alistair Francis New
[PULL,v2,33/42] target/riscv: Remove the hardcoded RVXLEN macro [PULL,v2,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 2 - --- 2021-05-05 Alistair Francis New
[PULL,v2,32/42] target/riscv: fix a typo with interrupt names [PULL,v2,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-05 Alistair Francis New
[PULL,v2,31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions [PULL,v2,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-05 Alistair Francis New
[PULL,v2,30/42] hw/riscv: Fix OT IBEX reset vector [PULL,v2,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 - --- 2021-05-05 Alistair Francis New
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