Show patches with: Submitter = Alistair Francis       |    State = Action Required       |   724 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,60/65] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update() [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,59/65] target/riscv: make CPUCFG() macro public [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,58/65] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,57/65] target/riscv: deprecate the 'any' CPU type [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 1 --- 2023-09-08 Alistair Francis New
[PULL,56/65] avocado, risc-v: add tuxboot tests for 'max' CPU [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 1 --- 2023-09-08 Alistair Francis New
[PULL,55/65] target/riscv: add 'max' CPU type [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,54/65] target/riscv/cpu.c: limit cfg->vext_spec log message [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,53/65] target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array() [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,52/65] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array() [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,51/65] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[] [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,50/65] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[] [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,49/65] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[] [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,48/65] target/riscv/cpu.c: split kvm prop handling to its own helper [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,47/65] target/riscv/cpu.c: skip 'bool' check when filtering KVM props [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,46/65] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,45/65] target/riscv: don't read CSR in riscv_csrrw_do64 [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,44/65] target/riscv: Align the AIA model to v1.0 ratified spec [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,43/65] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,42/65] target/riscv: Allocate itrigger timers only once [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,41/65] target/riscv: Use accelerated helper for AES64KS1I [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,40/65] linux-user/riscv: Add new extensions to hwprobe [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG 2 - - --- 2023-09-08 Alistair Francis New
[PULL,39/65] hw/intc/riscv_aplic.c fix non-KVM --enable-debug build [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,38/65] hw/riscv/virt.c: fix non-KVM --enable-debug build [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,37/65] riscv: zicond: make non-experimental [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,36/65] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0 [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,35/65] target/riscv: Update CSR bits name for svadu extension [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,34/65] hw/riscv: virt: Fix riscv,pmu DT node path [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG 1 1 - --- 2023-09-08 Alistair Francis New
[PULL,33/65] target/riscv: select KVM AIA in riscv virt machine [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,32/65] target/riscv: update APLIC and IMSIC to support KVM AIA [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,31/65] target/riscv: Create an KVM AIA irqchip [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,30/65] target/riscv: check the in-kernel irqchip support [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,29/65] target/riscv: support the AIA device emulation with KVM enabled [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,28/65] linux-user/riscv: Use abi type for target_ucontext [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,27/65] hw/intc: Make rtc variable names consistent [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,26/65] hw/intc: Fix upper/lower mtime write calculation [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,25/65] target/riscv: Fix zfa fleq.d and fltq.d [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,24/65] target/riscv: Add Zihintntl extension ISA string to DTS [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,23/65] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG 1 1 - --- 2023-09-08 Alistair Francis New
[PULL,22/65] target/riscv: Add Zvksed ISA extension support [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,21/65] crypto: Add SM4 constant parameter CK [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,20/65] crypto: Create sm4_subword [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,19/65] target/riscv: Add Zvkg ISA extension support [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,18/65] target/riscv: Add Zvksh ISA extension support [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,17/65] target/riscv: Add Zvknh ISA extension support [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,16/65] target/riscv: Add Zvkned ISA extension support [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,15/65] target/riscv: Add Zvbb ISA extension support [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,14/65] target/riscv: Refactor some of the generic vector functionality [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,13/65] target/riscv: Refactor translation of vector-widening instruction [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,12/65] target/riscv: Move vector translation checks [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,11/65] target/riscv: Add Zvbc ISA extension support [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - - - --- 2023-09-08 Alistair Francis New
[PULL,10/65] target/riscv: Remove redundant "cpu_vl == 0" checks [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG 1 1 - --- 2023-09-08 Alistair Francis New
[PULL,09/65] target/riscv: Refactor vector-vector translation macro [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,08/65] target/riscv: Refactor some of the generic vector functionality [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG 1 1 - --- 2023-09-08 Alistair Francis New
[PULL,07/65] target/riscv: Use existing lookup tables for MixColumns [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,06/65] target/riscv: Fix page_check_range use in fault-only-first [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 1 - --- 2023-09-08 Alistair Francis New
[PULL,05/65] target/riscv/cpu.c: add smepmp isa string [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,04/65] target/riscv/cpu.c: add zmmul isa string [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,03/65] hw/char/riscv_htif: Fix the console syscall on big endian hosts [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 3 - --- 2023-09-08 Alistair Francis New
[PULL,02/65] hw/char/riscv_htif: Fix printing of console characters on big endian hosts [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 4 - --- 2023-09-08 Alistair Francis New
[PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG - 2 - --- 2023-09-08 Alistair Francis New
[PULL,00/65] riscv-to-apply queue - - - --- 2023-09-08 Alistair Francis New
[PULL,2/2] hw/riscv/virt.c: change 'aclint' TCG check [PULL,1/2] target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids() - 2 - --- 2023-08-11 Alistair Francis New
[PULL,1/2] target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids() [PULL,1/2] target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids() 1 1 - --- 2023-08-11 Alistair Francis New
[PULL,0/2] riscv-to-apply queue - - - --- 2023-08-11 Alistair Francis New
[RFC,v1,3/3] hw: nvme: ctrl: Process SPDM requests Initial support for SPDM - - - --- 2023-08-08 Alistair Francis New
[RFC,v1,2/3] hw: nvme: ctrl: Initial support for DOE Initial support for SPDM - - - --- 2023-08-08 Alistair Francis New
[RFC,v1,1/3] subprojects: libspdm: Initial support Initial support for SPDM - - - --- 2023-08-08 Alistair Francis New
[PULL,1/1] roms/opensbi: Upgrade from v1.3 to v1.3.1 [PULL,1/1] roms/opensbi: Upgrade from v1.3 to v1.3.1 - 1 1 --- 2023-07-23 Alistair Francis New
[PULL,0/1] riscv-to-apply queue - - - --- 2023-07-23 Alistair Francis New
[PULL,5/5] target/riscv: Fix LMUL check to use VLEN [PULL,1/5] docs/system/target-riscv.rst: tidy CPU firmware section - 1 - --- 2023-07-19 Alistair Francis New
[PULL,4/5] hw/riscv: Fix typo field in error_report [PULL,1/5] docs/system/target-riscv.rst: tidy CPU firmware section - 1 - --- 2023-07-19 Alistair Francis New
[PULL,3/5] target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf [PULL,1/5] docs/system/target-riscv.rst: tidy CPU firmware section - 2 1 --- 2023-07-19 Alistair Francis New
[PULL,2/5] riscv/disas: Fix disas output of upper immediates [PULL,1/5] docs/system/target-riscv.rst: tidy CPU firmware section 1 - - --- 2023-07-19 Alistair Francis New
[PULL,1/5] docs/system/target-riscv.rst: tidy CPU firmware section [PULL,1/5] docs/system/target-riscv.rst: tidy CPU firmware section - 1 - --- 2023-07-19 Alistair Francis New
[PULL,0/5] riscv-to-apply queue - - - --- 2023-07-19 Alistair Francis New
[PULL,54/54] riscv: Add support for the Zfa extension [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 1 - --- 2023-07-10 Alistair Francis New
[PULL,53/54] target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 1 - --- 2023-07-10 Alistair Francis New
[PULL,52/54] target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,51/54] target/riscv: update multi-letter extension KVM properties [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,50/54] target/riscv/cpu.c: create KVM mock properties [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,49/54] target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext() [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,48/54] target/riscv/cpu.c: add satp_mode properties earlier [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 3 - --- 2023-07-10 Alistair Francis New
[PULL,47/54] target/riscv/kvm.c: add multi-letter extension KVM properties [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 1 - --- 2023-07-10 Alistair Francis New
[PULL,46/54] target/riscv/kvm.c: update KVM MISA bits [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 1 - --- 2023-07-10 Alistair Francis New
[PULL,45/54] target/riscv: add KVM specific MISA properties [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,44/54] target/riscv/cpu: add misa_ext_info_arr[] [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 3 - --- 2023-07-10 Alistair Francis New
[PULL,43/54] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 1 - --- 2023-07-10 Alistair Francis New
[PULL,42/54] target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 1 - --- 2023-07-10 Alistair Francis New
[PULL,41/54] target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids() [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 1 - --- 2023-07-10 Alistair Francis New
[PULL,40/54] target/riscv: use KVM scratch CPUs to init KVM properties [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 1 - --- 2023-07-10 Alistair Francis New
[PULL,39/54] target/riscv/cpu.c: restrict 'marchid' value [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,38/54] target/riscv/cpu.c: restrict 'mimpid' value [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,37/54] target/riscv/cpu.c: restrict 'mvendorid' value [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,36/54] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 3 - --- 2023-07-10 Alistair Francis New
[PULL,35/54] target/riscv: skip features setup for KVM CPUs [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,34/54] hw/riscv: virt: Convert fdt_load_addr to uint64_t [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,33/54] riscv: Generate devicetree only after machine initialization is complete [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,32/54] target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
[PULL,31/54] target/riscv: Add disas support for BF16 extensions [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble 1 - - --- 2023-07-10 Alistair Francis New
[PULL,30/54] target/riscv: Set the correct exception for implict G-stage translation fail [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble - 2 - --- 2023-07-10 Alistair Francis New
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