Show patches with: Series = riscv: sifive_u: Improve the emulation fidelity of sifive_u machine       |    State = Action Required       |   26 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v3,28/28] riscv: sifive_u: Update model and compatible strings in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - --- 2019-08-11 Bin Meng New
[v3,27/28] riscv: virt: Change create_fdt() to return void riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 3 - --- 2019-08-11 Bin Meng New
[v3,25/28] riscv: hw: Remove not needed PLIC properties in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 2 - --- 2019-08-11 Bin Meng New
[v3,24/28] riscv: sifive_u: Support loading initramfs riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 2 - --- 2019-08-11 Bin Meng New
[v3,23/28] riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - --- 2019-08-11 Bin Meng New
[v3,22/28] riscv: sifive_u: Generate an aliases node in the device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - --- 2019-08-11 Bin Meng New
[v3,21/28] riscv: sifive_u: Update UART and ethernet node clock properties riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - --- 2019-08-11 Bin Meng New
[v3,19/28] riscv: sifive_u: Instantiate OTP memory with a serial number riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - --- 2019-08-11 Bin Meng New
[v3,18/28] riscv: hw: Implement a model for SiFive FU540 OTP riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - --- 2019-08-11 Bin Meng New
[v3,17/28] riscv: sifive_u: Change UART node name in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - --- 2019-08-11 Bin Meng New
[v3,16/28] riscv: sifive_u: Add PRCI block to the SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - --- 2019-08-11 Bin Meng New
[v3,15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - --- 2019-08-11 Bin Meng New
[v3,14/28] riscv: sifive: Implement PRCI model for FU540 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - --- 2019-08-11 Bin Meng New
[v3,13/28] riscv: sifive_e: prci: Update the PRCI register block size riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 2 - --- 2019-08-11 Bin Meng New
[v3,12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 2 - --- 2019-08-11 Bin Meng New
[v3,11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - --- 2019-08-11 Bin Meng New
[v3,10/28] riscv: sifive_u: Remove the unnecessary include of prci header riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - --- 2019-08-11 Bin Meng New
[v3,09/28] riscv: sifive_u: Update UART base addresses and IRQs riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 2 - --- 2019-08-11 Bin Meng New
[v3,08/28] riscv: sifive_u: Update PLIC hart topology configuration string riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - --- 2019-08-11 Bin Meng New
[v3,07/28] riscv: sifive_u: Set the minimum number of cpus to 2 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - --- 2019-08-11 Bin Meng New
[v3,06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - --- 2019-08-11 Bin Meng New
[v3,05/28] riscv: hart: Support heterogeneous harts population riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - --- 2019-08-11 Bin Meng New
[v3,04/28] riscv: hart: Extract hart realize to a separate routine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - --- 2019-08-11 Bin Meng New
[v3,03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 2 - --- 2019-08-11 Bin Meng New
[v3,02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - --- 2019-08-11 Bin Meng New
[v3,01/28] riscv: hw: Remove superfluous "linux, phandle" property riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - --- 2019-08-11 Bin Meng New