Show patches with: Series = target/riscv: Improve RISC-V Debug support       |   8 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2,8/8] target/riscv: debug: Add initial support of type 6 trigger target/riscv: Improve RISC-V Debug support - 1 - --- 2022-09-09 Bin Meng New
[v2,7/8] target/riscv: debug: Check VU/VS modes for type 2 trigger target/riscv: Improve RISC-V Debug support - 1 - --- 2022-09-09 Bin Meng New
[v2,6/8] target/riscv: debug: Create common trigger actions function target/riscv: Improve RISC-V Debug support - 2 - --- 2022-09-09 Bin Meng New
[v2,5/8] target/riscv: debug: Introduce tinfo CSR target/riscv: Improve RISC-V Debug support - 2 - --- 2022-09-09 Bin Meng New
[v2,4/8] target/riscv: debug: Restrict the range of tselect value can be written target/riscv: Improve RISC-V Debug support - 2 - --- 2022-09-09 Bin Meng New
[v2,3/8] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs target/riscv: Improve RISC-V Debug support - 2 - --- 2022-09-09 Bin Meng New
[v2,2/8] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content target/riscv: Improve RISC-V Debug support - 2 - --- 2022-09-09 Bin Meng New
[v2,1/8] target/riscv: debug: Determine the trigger type from tdata1.type target/riscv: Improve RISC-V Debug support - 2 - --- 2022-09-09 Bin Meng New