Show patches with: Series = [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig       |   89 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,89/89] target/riscv: add Ventana's Veyron V1 CPU [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig 1 - - --- 2023-05-05 Alistair Francis New
[PULL,88/89] riscv: Make sure an exception is raised if a pte is malformed [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 1 - --- 2023-05-05 Alistair Francis New
[PULL,87/89] target/riscv: Fix Guest Physical Address Translation [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,86/89] target/riscv: Restore the predicate() NULL check behavior [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 4 - --- 2023-05-05 Alistair Francis New
[PULL,85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig 1 1 - --- 2023-05-05 Alistair Francis New
[PULL,84/89] target/riscv: add query-cpy-definitions support [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,83/89] target/riscv: add CPU QOM header [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,82/89] hw/intc/riscv_aplic: Zero init APLIC internal state [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,81/89] target/riscv: Reorg sum check in get_physical_address [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,80/89] target/riscv: Reorg access check in get_physical_address [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,79/89] target/riscv: Merge checks for reserved pte flags [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,78/89] target/riscv: Don't modify SUM with is_debug [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,77/89] target/riscv: Suppress pte update with is_debug [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,76/89] target/riscv: Move leaf pte processing out of level loop [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,75/89] target/riscv: Hoist pbmte and hade out of the level loop [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,74/89] target/riscv: Hoist second stage mode change to callers [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,73/89] target/riscv: Check SUM in the correct register [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,70/89] target/riscv: Introduce mmuidx_2stage [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,69/89] target/riscv: Introduce mmuidx_priv [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,68/89] target/riscv: Introduce mmuidx_sum [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,66/89] target/riscv: Handle HLV, HSV via helpers [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,64/89] target/riscv: Reduce overhead of MSTATUS_SUM change [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 4 1 --- 2023-05-05 Alistair Francis New
[PULL,63/89] target/riscv: Separate priv from mmu_idx [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 4 1 --- 2023-05-05 Alistair Francis New
[PULL,62/89] target/riscv: Add a tb flags field for vstart [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 1 --- 2023-05-05 Alistair Francis New
[PULL,61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 1 --- 2023-05-05 Alistair Francis New
[PULL,60/89] target/riscv: Encode the FS and VS on a normal way for tb flags [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 1 --- 2023-05-05 Alistair Francis New
[PULL,59/89] target/riscv: Add a general status enum for extensions [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 1 --- 2023-05-05 Alistair Francis New
[PULL,58/89] target/riscv: Extract virt enabled state from tb flags [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 1 --- 2023-05-05 Alistair Francis New
[PULL,57/89] target/riscv: fix H extension TVM trap [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 - --- 2023-05-05 Alistair Francis New
[PULL,56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig 1 - - --- 2023-05-05 Alistair Francis New
[PULL,55/89] target/riscv: Legalize MPP value in write_mstatus [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,54/89] target/riscv: Use PRV_RESERVED instead of PRV_H [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,53/89] target/riscv: Fix the mstatus.MPP value after executing MRET [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 1 - --- 2023-05-05 Alistair Francis New
[PULL,52/89] target/riscv/cpu.c: redesign register_cpu_props() [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,51/89] target/riscv: add RVG and remove cpu->cfg.ext_g [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,49/89] target/riscv: remove riscv_cpu_sync_misa_cfg() [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,48/89] target/riscv: remove cpu->cfg.ext_v [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,47/89] target/riscv: remove cpu->cfg.ext_j [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,46/89] target/riscv: remove cpu->cfg.ext_h [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,45/89] target/riscv: remove cpu->cfg.ext_u [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,44/89] target/riscv: remove cpu->cfg.ext_s [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,43/89] target/riscv: remove cpu->cfg.ext_m [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,42/89] target/riscv: remove cpu->cfg.ext_e [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,41/89] target/riscv: remove cpu->cfg.ext_i [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,40/89] target/riscv: remove cpu->cfg.ext_f [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,39/89] target/riscv: remove cpu->cfg.ext_d [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,38/89] target/riscv: remove cpu->cfg.ext_c [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,37/89] target/riscv: remove cpu->cfg.ext_a [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,36/89] target/riscv: introduce riscv_cpu_add_misa_properties() [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,35/89] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,34/89] target/riscv: remove MISA properties from isa_edata_arr[] [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,33/89] target/riscv: sync env->misa_ext* with cpu->cfg in realize() [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,32/89] hw/riscv: Add signature dump function for spike to run ACT tests [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,31/89] target/riscv: Fix lines with over 80 characters [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig 1 2 - --- 2023-05-05 Alistair Francis New
[PULL,30/89] target/riscv: Fix format for comments [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig 1 3 - --- 2023-05-05 Alistair Francis New
[PULL,29/89] target/riscv: Fix format for indentation [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig 1 2 - --- 2023-05-05 Alistair Francis New
[PULL,28/89] target/riscv: Remove riscv_cpu_virt_enabled() [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 4 - --- 2023-05-05 Alistair Francis New
[PULL,27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig 1 1 - --- 2023-05-05 Alistair Francis New
[PULL,26/89] target/riscv: Fix addr type for get_physical_address [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,25/89] target/riscv: Remove redundant parentheses [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 - --- 2023-05-05 Alistair Francis New
[PULL,24/89] target/riscv: Convert env->virt to a bool env->virt_enabled [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 - --- 2023-05-05 Alistair Francis New
[PULL,23/89] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 - --- 2023-05-05 Alistair Francis New
[PULL,22/89] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 - --- 2023-05-05 Alistair Francis New
[PULL,21/89] target/riscv: Remove redundant check on RVH [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 - --- 2023-05-05 Alistair Francis New
[PULL,20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 - --- 2023-05-05 Alistair Francis New
[PULL,19/89] target/riscv: Fix itrigger when icount is used [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig 1 1 - --- 2023-05-05 Alistair Francis New
[PULL,18/89] target/riscv: Add support for Zce [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 1 - --- 2023-05-05 Alistair Francis New
[PULL,17/89] disas/riscv.c: add disasm support for Zc* [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig 1 - - --- 2023-05-05 Alistair Francis New
[PULL,16/89] target/riscv: expose properties for Zc* extension [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 1 - --- 2023-05-05 Alistair Francis New
[PULL,15/89] target/riscv: add support for Zcmt extension [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,14/89] target/riscv: add support for Zcmp extension [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,13/89] target/riscv: add support for Zcb extension [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,12/89] target/riscv: add support for Zcd extension [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,11/89] target/riscv: add support for Zcf extension [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,10/89] target/riscv: add support for Zca extension [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 - --- 2023-05-05 Alistair Francis New
[PULL,09/89] target/riscv: add cfg properties for Zc* extension [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 1 - --- 2023-05-05 Alistair Francis New
[PULL,07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig 1 1 - --- 2023-05-05 Alistair Francis New
[PULL,06/89] target/riscv: refactor Zicond support [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig 1 1 - --- 2023-05-05 Alistair Francis New
[PULL,05/89] target/riscv: Simplify arguments for riscv_csrrw_check [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 - --- 2023-05-05 Alistair Francis New
[PULL,04/89] target/riscv: Simplify type conversion for CPURISCVState [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,03/89] target/riscv: Simplify getting RISCVCPU pointer from env [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 - --- 2023-05-05 Alistair Francis New
[PULL,02/89] target/riscv: Fix priv version dependency for vector and zfh [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New