Show patches with: Submitter = Jim Shu       |    State = Action Required       |   52 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v4,3/3] hw/riscv: Add the checking if DTB overlaps to kernel or initrd Support 64-bit address of initrd - - - --- 2024-11-20 Jim Shu New
[v4,2/3] hw/riscv: Add a new struct RISCVBootInfo Support 64-bit address of initrd - - - --- 2024-11-20 Jim Shu New
[v4,1/3] hw/riscv: Support to load DTB after 3GB memory on 64-bit system. Support 64-bit address of initrd - - - --- 2024-11-20 Jim Shu New
[v3,3/3] hw/riscv: Add the checking if DTB overlaps to kernel or initrd Support 64-bit address of initrd - 1 - --- 2024-11-08 Jim Shu New
[v3,2/3] hw/riscv: Add a new struct RISCVBootInfo Support 64-bit address of initrd - - - --- 2024-11-08 Jim Shu New
[v3,1/3] hw/riscv: Support to load DTB after 3GB memory on 64-bit system. Support 64-bit address of initrd - - - --- 2024-11-08 Jim Shu New
[v2,3/3] hw/riscv: Add the checking if DTB overlaps to kernel or initrd Support 64-bit address of initrd - - - --- 2024-11-07 Jim Shu New
[v2,2/3] hw/riscv: Add a new struct RISCVBootInfo Support 64-bit address of initrd - - - --- 2024-11-07 Jim Shu New
[v2,1/3] hw/riscv: Support to load DTB after 3GB memory on 64-bit system. Support 64-bit address of initrd - 1 - --- 2024-11-07 Jim Shu New
[2/2] hw/riscv: Support different address-cells for initrd Support 64-bit address of initrd - - - --- 2024-10-21 Jim Shu New
[1/2] hw/riscv: Support to load DTB after 3GB memory on 64-bit system. Support 64-bit address of initrd - - - --- 2024-10-21 Jim Shu New
vfio/pci: Fix null pointer deference from error API vfio/pci: Fix null pointer deference from error API - - - --- 2024-09-12 Jim Shu New
[v2,3/3] hw/net: xilinx_axienet: Fix DMA RX IRQ if ethernet disable RX Several fixes of AXI-ethernet/DMA - 1 - --- 2024-08-01 Jim Shu New
[v2,2/3] hw/dma: xilinx_axidma: Send DMA error IRQ if any memory access is failed Several fixes of AXI-ethernet/DMA - - - --- 2024-08-01 Jim Shu New
[v2,1/3] hw/dma: xilinx_axidma: Correct the txlen value in the descriptor Several fixes of AXI-ethernet/DMA - 1 - --- 2024-08-01 Jim Shu New
[4/4] hw/net: xilinx_axienet: Fix DMA RX IRQ if ethernet disable RX Several fixes of AXI-ethernet/DMA - - - --- 2024-07-26 Jim Shu New
[3/4] hw/dma: xilinx_axidma: Reset qemu_irq when DMA/Stream is reset Several fixes of AXI-ethernet/DMA - - - --- 2024-07-26 Jim Shu New
[2/4] hw/dma: xilinx_axidma: Send DMA error IRQ if any memory access is failed Several fixes of AXI-ethernet/DMA - - - --- 2024-07-26 Jim Shu New
[1/4] hw/dma: xilinx_axidma: Correct the txlen value in the descriptor Several fixes of AXI-ethernet/DMA - - - --- 2024-07-26 Jim Shu New
[2/2] linux-user: Add QEMU include path to vdso Let gen-vdso tool to use internal ELF header - - - --- 2024-07-26 Jim Shu New
[1/2] include/elf.h: align ELF macro name with glibc Let gen-vdso tool to use internal ELF header - 1 - --- 2024-07-26 Jim Shu New
[RFC,16/16] hw/riscv: virt: Add WorldGuard support Implements RISC-V WorldGuard extension v0.4 - - - --- 2024-06-12 Jim Shu New
[RFC,15/16] hw/misc: riscv_wgchecker: Check the slot settings in translate Implements RISC-V WorldGuard extension v0.4 - - - --- 2024-06-12 Jim Shu New
[RFC,14/16] hw/misc: riscv_wgchecker: Implement correct block-access behavior Implements RISC-V WorldGuard extension v0.4 - - - --- 2024-06-12 Jim Shu New
[RFC,13/16] hw/misc: riscv_wgchecker: Implement wgchecker slot registers Implements RISC-V WorldGuard extension v0.4 - - - --- 2024-06-12 Jim Shu New
[RFC,12/16] hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker Implements RISC-V WorldGuard extension v0.4 - - - --- 2024-06-12 Jim Shu New
[RFC,11/16] hw/misc: riscv_worldguard: Add API to enable WG extension of CPU Implements RISC-V WorldGuard extension v0.4 - - - --- 2024-06-12 Jim Shu New
[RFC,10/16] target/riscv: Add WID to MemTxAttrs of CPU memory transactions Implements RISC-V WorldGuard extension v0.4 - - - --- 2024-06-12 Jim Shu New
[RFC,09/16] target/riscv: Implement WorldGuard CSRs Implements RISC-V WorldGuard extension v0.4 - - - --- 2024-06-12 Jim Shu New
[RFC,08/16] target/riscv: Allow global WG config to set WG CPU callbacks Implements RISC-V WorldGuard extension v0.4 - - - --- 2024-06-12 Jim Shu New
[RFC,07/16] target/riscv: Add defines for WorldGuard CSRs Implements RISC-V WorldGuard extension v0.4 - - - --- 2024-06-12 Jim Shu New
[RFC,06/16] target/riscv: Add hard-coded CPU state of WG extension Implements RISC-V WorldGuard extension v0.4 - - - --- 2024-06-12 Jim Shu New
[RFC,05/16] target/riscv: Add CPU options of WorldGuard CPU extension Implements RISC-V WorldGuard extension v0.4 - - - --- 2024-06-12 Jim Shu New
[RFC,04/16] hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config Implements RISC-V WorldGuard extension v0.4 - - - --- 2024-06-12 Jim Shu New
[RFC,03/16] exec: Add RISC-V WorldGuard WID to MemTxAttrs Implements RISC-V WorldGuard extension v0.4 - - - --- 2024-06-12 Jim Shu New
[RFC,02/16] accel/tcg: memory access from CPU will pass access_type to IOMMU Implements RISC-V WorldGuard extension v0.4 - - - --- 2024-06-12 Jim Shu New
[RFC,01/16] accel/tcg: Store section pointer in CPUTLBEntryFull Implements RISC-V WorldGuard extension v0.4 - - - --- 2024-06-12 Jim Shu New
target/riscv: support atomic instruction fetch (Ziccif) target/riscv: support atomic instruction fetch (Ziccif) - 1 - --- 2024-06-07 Jim Shu New
[2/2] target/riscv: Make the "virt" register writable by GDB [1/2] target/riscv: Expose "virt" register for GDB for reads - 2 - --- 2023-03-05 Jim Shu New
[1/2] target/riscv: Expose "virt" register for GDB for reads [1/2] target/riscv: Expose "virt" register for GDB for reads - 3 - --- 2023-03-05 Jim Shu New
hw/intc: sifive_plic: fix out-of-bound access of source_priority array hw/intc: sifive_plic: fix out-of-bound access of source_priority array - 1 - --- 2022-11-27 Jim Shu New
target/riscv: support cache-related PMU events in virtual mode target/riscv: support cache-related PMU events in virtual mode - 1 - --- 2022-11-23 Jim Shu New
[v3,2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field Enhance maximum priority support of PLIC 1 1 - --- 2022-10-03 Jim Shu New
[v3,1/2] hw/intc: sifive_plic: fix hard-coded max priority level Enhance maximum priority support of PLIC 1 1 - --- 2022-10-03 Jim Shu New
[v2,2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field Enhance maximum priority support of PLIC - - - --- 2022-09-30 Jim Shu New
[v2,1/2] hw/intc: sifive_plic: fix hard-coded max priority level Enhance maximum priority support of PLIC - 1 - --- 2022-09-30 Jim Shu New
hw/intc: sifive_plic: fix hard-coded max priority level hw/intc: sifive_plic: fix hard-coded max priority level - 1 - --- 2022-09-25 Jim Shu New
target/riscv: Support SW update of PTE A/D bits and Ssptwad extension target/riscv: Support SW update of PTE A/D bits and Ssptwad extension - 1 - --- 2022-07-18 Jim Shu New
[v2,2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers Align SiFive PDMA behavior to real hardware - 4 1 --- 2022-01-04 Jim Shu New
[v2,1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register Align SiFive PDMA behavior to real hardware - 3 1 --- 2022-01-04 Jim Shu New
[2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers Align SiFive PDMA behavior to real hardware - 4 1 --- 2021-12-28 Jim Shu New
[1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register Align SiFive PDMA behavior to real hardware - 3 1 --- 2021-12-28 Jim Shu New