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«
1
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3052
3053
»
Patch
Series
A/R/T
S/W/F
Date
Submitter
Delegate
State
[v3,5/5] tests: Add migration test for loongarch64
Add migration test for loongarch64
2 1 -
-
-
-
2024-05-06
Bibo Mao
New
[v3,4/5] hw/loongarch: Set minimium memory size as 256M
Add migration test for loongarch64
- - -
-
-
-
2024-05-06
Bibo Mao
New
[v3,3/5] hw/loongarch: Add compat machine for 9.0
Add migration test for loongarch64
- - -
-
-
-
2024-05-06
Bibo Mao
New
[v3,2/5] hw/loongarch: Rename LoongArchMachineState with VirtMachineState
Add migration test for loongarch64
- - -
-
-
-
2024-05-06
Bibo Mao
New
[v3,1/5] hw/loongarch: Rename LOONGARCH_MACHINE with VIRT_MACHINE
Add migration test for loongarch64
- - -
-
-
-
2024-05-06
Bibo Mao
New
[PULL,15/15] Hexagon (target/hexagon) Remove hex_common.read_attribs_file
[PULL,01/15] Hexagon (target/hexagon) Analyze reads before writes
- 2 -
-
-
-
2024-05-06
Brian Cain
New
[PULL,14/15] Hexagon (target/hexagon) Remove gen_shortcode.py
[PULL,01/15] Hexagon (target/hexagon) Analyze reads before writes
- 2 -
-
-
-
2024-05-06
Brian Cain
New
[PULL,13/15] Hexagon (target/hexagon) Remove gen_op_regs.py
[PULL,01/15] Hexagon (target/hexagon) Analyze reads before writes
- 1 -
-
-
-
2024-05-06
Brian Cain
New
[PULL,12/15] Hexagon (target/hexagon) Remove uses of op_regs_generated.h.inc
[PULL,01/15] Hexagon (target/hexagon) Analyze reads before writes
- 1 -
-
-
-
2024-05-06
Brian Cain
New
[PULL,11/15] Hexagon (tests/tcg/hexagon) Test HVX .new read from high half of pair
[PULL,01/15] Hexagon (target/hexagon) Analyze reads before writes
- 1 -
-
-
-
2024-05-06
Brian Cain
New
[PULL,10/15] Hexagon (target/hexagon) Mark has_pred_dest in trans functions
[PULL,01/15] Hexagon (target/hexagon) Analyze reads before writes
- 1 -
-
-
-
2024-05-06
Brian Cain
New
[PULL,09/15] Hexagon (target/hexagon) Mark dest_idx in trans functions
[PULL,01/15] Hexagon (target/hexagon) Analyze reads before writes
- 1 -
-
-
-
2024-05-06
Brian Cain
New
[PULL,08/15] Hexagon (target/hexagon) Mark new_read_idx in trans functions
[PULL,01/15] Hexagon (target/hexagon) Analyze reads before writes
- 1 -
-
-
-
2024-05-06
Brian Cain
New
[PULL,07/15] Hexagon (target/hexagon) Add is_old/is_new to Register class
[PULL,01/15] Hexagon (target/hexagon) Analyze reads before writes
- 2 -
-
-
-
2024-05-06
Brian Cain
New
[PULL,06/15] Hexagon (target/hexagon) Only pass env to generated helper when needed
[PULL,01/15] Hexagon (target/hexagon) Analyze reads before writes
- 1 1
-
-
-
2024-05-06
Brian Cain
New
[PULL,05/15] Hexagon (target/hexagon) Pass SP explicitly to helpers that need it
[PULL,01/15] Hexagon (target/hexagon) Analyze reads before writes
- 2 1
-
-
-
2024-05-06
Brian Cain
New
[PULL,04/15] Hexagon (target/hexagon) Pass P0 explicitly to helpers that need it
[PULL,01/15] Hexagon (target/hexagon) Analyze reads before writes
- 2 1
-
-
-
2024-05-06
Brian Cain
New
[PULL,03/15] Hexagon (target/hexagon) Enable more short-circuit packets (HVX)
[PULL,01/15] Hexagon (target/hexagon) Analyze reads before writes
- 1 -
-
-
-
2024-05-06
Brian Cain
New
[PULL,02/15] Hexagon (target/hexagon) Enable more short-circuit packets (scalar core)
[PULL,01/15] Hexagon (target/hexagon) Analyze reads before writes
- 1 -
-
-
-
2024-05-06
Brian Cain
New
[PULL,01/15] Hexagon (target/hexagon) Analyze reads before writes
[PULL,01/15] Hexagon (target/hexagon) Analyze reads before writes
- 1 -
-
-
-
2024-05-06
Brian Cain
New
[PULL,00/15] Hexagon: simplify gen for packets w/o read-after-write
- - -
-
-
-
2024-05-06
Brian Cain
New
[v5] target/riscv: Implement dynamic establishment of custom decoder
[v5] target/riscv: Implement dynamic establishment of custom decoder
- 2 -
-
-
-
2024-05-06
Huang Tao
New
[v4] target/loongarch: Add TCG macro in structure CPUArchState
[v4] target/loongarch: Add TCG macro in structure CPUArchState
- 1 -
-
-
-
2024-05-06
Bibo Mao
New
[57/57] target/arm: Convert SQDMULH, SQRDMULH to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[56/57] target/arm: Tidy SQDMULH, SQRDMULH (vector)
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[55/57] target/arm: Convert MLA, MLS to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[54/57] target/arm: Convert MUL, PMUL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[53/57] target/arm: Convert SABA, SABD, UABA, UABD to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[52/57] target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[51/57] target/arm: Convert SRHADD, URHADD to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[50/57] target/arm: Convert SRHADD, URHADD to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[49/57] target/arm: Convert SHSUB, UHSUB to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[48/57] target/arm: Convert SHSUB, UHSUB to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[47/57] target/arm: Convert SHADD, UHADD to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[46/57] target/arm: Convert SHADD, UHADD to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[45/57] target/arm: Use TCG_COND_TSTNE in gen_cmtst_{i32,i64}
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[44/57] target/arm: Convert CMGT, CMHI, CMGE, CMHS, CMTST, CMEQ to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[43/57] target/arm: Convert ADD, SUB (vector) to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[42/57] target/arm: Convert SQRSHL, UQRSHL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[41/57] target/arm: Convert SQRSHL and UQRSHL (register) to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[40/57] target/arm: Convert SQSHL, UQSHL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[39/57] target/arm: Convert SQSHL and UQSHL (register) to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[38/57] target/arm: Convert SRSHL, URSHL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[37/57] target/arm: Convert SRSHL and URSHL (register) to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[36/57] target/arm: Convert SSHL, USHL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[35/57] target/arm: Convert SUQADD, USQADD to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[34/57] target/arm: Convert SQADD, SQSUB, UQADD, UQSUB to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[33/57] target/arm: Inline scalar SQADD, UQADD, SQSUB, UQSUB
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[32/57] target/arm: Inline scalar SUQADD and USQADD
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[31/57] target/arm: Convert SUQADD and USQADD to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[30/57] target/arm: Improve vector UQADD, UQSUB, SQADD, SQSUB
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[29/57] target/arm: Convert disas_simd_3same_logic to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[28/57] target/arm: Convert FMLAL, FMLSL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[27/57] target/arm: Use gvec for neon pmax, pmin
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[26/57] target/arm: Convert SMAXP, SMINP, UMAXP, UMINP to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[25/57] target/arm: Use gvec for neon padd
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[24/57] target/arm: Convert ADDP to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[23/57] target/arm: Use gvec for neon faddp, fmaxp, fminp
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[22/57] target/arm: Convert FMAXP, FMINP, FMAXNMP, FMINNMP to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[21/57] target/arm: Convert FADDP to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[20/57] target/arm: Convert FRECPS, FRSQRTS to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[19/57] target/arm: Convert FABD to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[18/57] target/arm: Convert FCMEQ, FCMGE, FCMGT, FACGE, FACGT to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[17/57] target/arm: Convert FMLA, FMLS to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[16/57] target/arm: Convert FNMUL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[15/57] target/arm: Expand vfp neg and abs inline
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[14/57] target/arm: Convert FMAX, FMIN, FMAXNM, FMINNM to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[13/57] target/arm: Convert FADD, FSUB, FDIV, FMUL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[12/57] target/arm: Convert FMULX to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[11/57] target/arm: Convert Advanced SIMD copy to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[10/57] target/arm: Convert XAR to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[09/57] target/arm: Convert Cryptographic 3-register, imm2 to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[08/57] target/arm: Convert Cryptographic 4-register to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[07/57] target/arm: Convert Cryptographic 2-register SHA512 to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[06/57] target/arm: Convert Cryptographic 3-register SHA512 to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[05/57] target/arm: Convert Cryptographic 2-register SHA to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[04/57] target/arm: Convert Cryptographic 3-register SHA to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[03/57] target/arm: Convert Cryptographic AES to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[02/57] target/arm: Split out gengvec64.c
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[01/57] target/arm: Split out gengvec.c
target/arm: Convert a64 advsimd to decodetree (part 1)
- - -
-
-
-
2024-05-06
Richard Henderson
New
[v3,3/3] Do not access /dev/mem in MSI-X PCI passthrough on Xen
Fix MSI-X handling for Xen HVM
- - -
-
-
-
2024-05-06
Marek Marczykowski-Górecki
New
[v3,2/3] Update Xen's features.h header
Fix MSI-X handling for Xen HVM
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2024-05-06
Marek Marczykowski-Górecki
New
[v3,1/3] hw/xen/xen_pt: Save back data only for declared registers
Fix MSI-X handling for Xen HVM
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2024-05-06
Marek Marczykowski-Górecki
New
[sdl-qemu,v1] /hw/intc/arm_gic WRONG ARGUMENTS
[sdl-qemu,v1] /hw/intc/arm_gic WRONG ARGUMENTS
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2024-05-05
Andrey Shumilin
New
[7/7] net/can: Remove unused struct 'CanBusState'
Remove some unused structures
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2024-05-05
Dr. David Alan Gilbert
New
[6/7] target/ppc: Remove unused struct 'mmu_ctx_hash32'
Remove some unused structures
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2024-05-05
Dr. David Alan Gilbert
New
[5/7] hw/arm/bcm2836: Remove unusued struct 'BCM283XClass'
Remove some unused structures
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2024-05-05
Dr. David Alan Gilbert
New
[4/7] hw/usb/dev-network: Remove unused struct 'rndis_config_parameter'
Remove some unused structures
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2024-05-05
Dr. David Alan Gilbert
New
[3/7] linux-user: sparc: Remove unused struct 'target_mc_fq'
Remove some unused structures
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2024-05-05
Dr. David Alan Gilbert
New
[2/7] linux-user: i386/signal: Remove unused fp structs
Remove some unused structures
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2024-05-05
Dr. David Alan Gilbert
New
[1/7] linux-user: cris: Remove unused struct 'rt_signal_frame'
Remove some unused structures
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2024-05-05
Dr. David Alan Gilbert
New
hw/char: Correct STM32L4x5 usart register CR2 field ADD_0 size
hw/char: Correct STM32L4x5 usart register CR2 field ADD_0 size
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2024-05-05
Inès Varhol
New
[4/4] tests/qtest: Check STM32L4x5 clock connections
Check clock connection between STM32L4x5 RCC and peripherals
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2024-05-05
Inès Varhol
New
[3/4] hw/char: Add QOM property for STM32L4x5 USART clock frequency
Check clock connection between STM32L4x5 RCC and peripherals
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2024-05-05
Inès Varhol
New
[2/4] hw/gpio: Handle clock migration in STM32L4x5 gpios
Check clock connection between STM32L4x5 RCC and peripherals
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2024-05-05
Inès Varhol
New
[1/4] hw/misc: Create STM32L4x5 SYSCFG clock
Check clock connection between STM32L4x5 RCC and peripherals
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2024-05-05
Inès Varhol
New
include/exec/cpu-common.h: Rename PAGE_BITS macro to PAGE_RWX
include/exec/cpu-common.h: Rename PAGE_BITS macro to PAGE_RWX
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2024-05-05
BALATON Zoltan
New
[v2] MAINTAINERS: Update my email address
[v2] MAINTAINERS: Update my email address
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2024-05-05
Bin Meng
New
[v10,10/10] virtio-gpu: Support Venus context
Support blob memory and venus on qemu
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2024-05-04
Dmitry Osipenko
New
[v10,09/10] virtio-gpu: Register capsets dynamically
Support blob memory and venus on qemu
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2024-05-04
Dmitry Osipenko
New
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