Show patches with: Submitter = Alistair Francis       |    State = Action Required       |   695 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,00/54] riscv-to-apply queue - - - --- 2023-07-10 Alistair Francis New
[PULL,60/60] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only. [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero 1 2 - --- 2023-06-14 Alistair Francis New
[PULL,59/60] target/riscv: Smepmp: Return error when access permission not allowed in PMP [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,58/60] target/riscv/vector_helper.c: Remove the check for extra tail elements [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,57/60] target/riscv/vector_helper.c: clean up reference of MTYPE [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,56/60] target/riscv: Fix initialized value for cur_pmmask [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 1 - --- 2023-06-14 Alistair Francis New
[PULL,55/60] util/log: Add vector registers to log [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 1 - --- 2023-06-14 Alistair Francis New
[PULL,54/60] docs/system: riscv: Add pflash usage details [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,53/60] riscv/virt: Support using pflash via -blockdev option [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 1 --- 2023-06-14 Alistair Francis New
[PULL,52/60] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none" [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 1 1 --- 2023-06-14 Alistair Francis New
[PULL,51/60] target/riscv: Remove pc_succ_insn from DisasContext [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,50/60] target/riscv: Enable PC-relative translation [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,49/60] target/riscv: Use true diff for gen_pc_plus_diff [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,48/60] target/riscv: Change gen_set_pc_imm to gen_update_pc [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,47/60] target/riscv: Change gen_goto_tb to work on displacements [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,46/60] target/riscv: Introduce cur_insn_len into DisasContext [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,45/60] target/riscv: Fix target address to update badaddr [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,44/60] disas/riscv.c: Remove redundant parentheses [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero 1 1 - --- 2023-06-14 Alistair Francis New
[PULL,43/60] disas/riscv.c: Fix lines with over 80 characters [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero 1 1 - --- 2023-06-14 Alistair Francis New
[PULL,42/60] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero 1 1 - --- 2023-06-14 Alistair Francis New
[PULL,41/60] disas/riscv.c: Support disas for Z*inx extensions [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,40/60] disas/riscv.c: Support disas for Zcm* extensions [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,39/60] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,38/60] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,37/60] disas: Change type of disassemble_info.target_info to pointer [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,36/60] target/riscv: smstateen knobs [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,35/60] target/riscv: Reuse tb->flags.FS [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,34/60] target/riscv: smstateen check for fcsr [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,33/60] target/riscv: Update cur_pmmask/base when xl changes [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 1 - --- 2023-06-14 Alistair Francis New
[PULL,32/60] target/riscv: Fix pointer mask transformation for vector address [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,31/60] hw/riscv: qemu crash when NUMA nodes exceed available CPUs [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 4 - --- 2023-06-14 Alistair Francis New
[PULL,30/60] hw/riscv/opentitan: Correct OpenTitanState parent type/size [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,29/60] hw/riscv/opentitan: Explicit machine type definition [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,28/60] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,27/60] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,26/60] hw/riscv/opentitan: Rename machine_[class]_init() functions [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,25/60] target/riscv: Deny access if access is partially inside the PMP entry [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 1 - --- 2023-06-14 Alistair Francis New
[PULL,24/60] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 1 - --- 2023-06-14 Alistair Francis New
[PULL,23/60] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,22/60] target/riscv: Flush TLB when pmpaddr is updated [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,21/60] target/riscv: Update the next rule addr in pmpaddr_csr_write() [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 1 - --- 2023-06-14 Alistair Francis New
[PULL,20/60] target/riscv: Flush TLB when MMWP or MML bits are changed [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 1 - --- 2023-06-14 Alistair Francis New
[PULL,19/60] target/riscv: Remove unused paramters in pmp_hart_has_privs_default() [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 1 - --- 2023-06-14 Alistair Francis New
[PULL,18/60] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 1 - --- 2023-06-14 Alistair Francis New
[PULL,17/60] target/riscv: Change the return type of pmp_hart_has_privs() to bool [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 1 - --- 2023-06-14 Alistair Francis New
[PULL,16/60] target/riscv: Make the short cut really work in pmp_hart_has_privs [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 1 - --- 2023-06-14 Alistair Francis New
[PULL,15/60] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,14/60] target/riscv: Update pmp_get_tlb_size() [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,13/60] target/riscv: rework write_misa() [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 1 - --- 2023-06-14 Alistair Francis New
[PULL,12/60] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 3 - --- 2023-06-14 Alistair Francis New
[PULL,11/60] target/riscv/cpu.c: validate extensions before riscv_timer_init() [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 3 - --- 2023-06-14 Alistair Francis New
[PULL,10/60] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 3 - --- 2023-06-14 Alistair Francis New
[PULL,09/60] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 3 - --- 2023-06-14 Alistair Francis New
[PULL,08/60] target/riscv: Update check for Zca/Zcf/Zcd [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 1 - --- 2023-06-14 Alistair Francis New
[PULL,07/60] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv versi… [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero 1 1 - --- 2023-06-14 Alistair Francis New
[PULL,06/60] target/riscv: add PRIV_VERSION_LATEST [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 4 - --- 2023-06-14 Alistair Francis New
[PULL,05/60] target/riscv/cpu.c: remove set_priv_version() [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 3 - --- 2023-06-14 Alistair Francis New
[PULL,04/60] target/riscv/cpu.c: remove set_vext_version() [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 3 - --- 2023-06-14 Alistair Francis New
[PULL,03/60] target/riscv/cpu.c: add riscv_cpu_validate_v() [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 3 - --- 2023-06-14 Alistair Francis New
[PULL,02/60] target/riscv: Move zc* out of the experimental properties [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero - 2 - --- 2023-06-14 Alistair Francis New
[PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero 1 2 - --- 2023-06-14 Alistair Francis New
[PULL,00/60] riscv-to-apply queue - - - --- 2023-06-14 Alistair Francis New
[PULL,89/89] target/riscv: add Ventana's Veyron V1 CPU [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig 1 - - --- 2023-05-05 Alistair Francis New
[PULL,88/89] riscv: Make sure an exception is raised if a pte is malformed [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 1 - --- 2023-05-05 Alistair Francis New
[PULL,87/89] target/riscv: Fix Guest Physical Address Translation [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,86/89] target/riscv: Restore the predicate() NULL check behavior [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 4 - --- 2023-05-05 Alistair Francis New
[PULL,85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig 1 1 - --- 2023-05-05 Alistair Francis New
[PULL,84/89] target/riscv: add query-cpy-definitions support [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,83/89] target/riscv: add CPU QOM header [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,82/89] hw/intc/riscv_aplic: Zero init APLIC internal state [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,81/89] target/riscv: Reorg sum check in get_physical_address [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,80/89] target/riscv: Reorg access check in get_physical_address [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,79/89] target/riscv: Merge checks for reserved pte flags [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,78/89] target/riscv: Don't modify SUM with is_debug [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,77/89] target/riscv: Suppress pte update with is_debug [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,76/89] target/riscv: Move leaf pte processing out of level loop [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,75/89] target/riscv: Hoist pbmte and hade out of the level loop [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,74/89] target/riscv: Hoist second stage mode change to callers [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,73/89] target/riscv: Check SUM in the correct register [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,70/89] target/riscv: Introduce mmuidx_2stage [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,69/89] target/riscv: Introduce mmuidx_priv [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,68/89] target/riscv: Introduce mmuidx_sum [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,66/89] target/riscv: Handle HLV, HSV via helpers [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 1 --- 2023-05-05 Alistair Francis New
[PULL,64/89] target/riscv: Reduce overhead of MSTATUS_SUM change [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 4 1 --- 2023-05-05 Alistair Francis New
[PULL,63/89] target/riscv: Separate priv from mmu_idx [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 4 1 --- 2023-05-05 Alistair Francis New
[PULL,62/89] target/riscv: Add a tb flags field for vstart [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 1 --- 2023-05-05 Alistair Francis New
[PULL,61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 1 --- 2023-05-05 Alistair Francis New
[PULL,60/89] target/riscv: Encode the FS and VS on a normal way for tb flags [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 1 --- 2023-05-05 Alistair Francis New
[PULL,59/89] target/riscv: Add a general status enum for extensions [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 1 --- 2023-05-05 Alistair Francis New
[PULL,58/89] target/riscv: Extract virt enabled state from tb flags [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 1 --- 2023-05-05 Alistair Francis New
[PULL,57/89] target/riscv: fix H extension TVM trap [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 3 - --- 2023-05-05 Alistair Francis New
[PULL,56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig 1 - - --- 2023-05-05 Alistair Francis New
[PULL,55/89] target/riscv: Legalize MPP value in write_mstatus [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,54/89] target/riscv: Use PRV_RESERVED instead of PRV_H [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
[PULL,53/89] target/riscv: Fix the mstatus.MPP value after executing MRET [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 1 - --- 2023-05-05 Alistair Francis New
[PULL,52/89] target/riscv/cpu.c: redesign register_cpu_props() [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig - 2 - --- 2023-05-05 Alistair Francis New
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