diff mbox series

[v2,4/7] target/mips: Fix insert.<b|h|w> for MIPS big endian host

Message ID 1553525566-14913-5-git-send-email-mateja.marjanovic@rt-rk.com (mailing list archive)
State New, archived
Headers show
Series target/mips: Add support for MSA instructions on a big endian host | expand

Commit Message

Mateja Marjanovic March 25, 2019, 2:52 p.m. UTC 
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>

Inserting from GPR to an element in a MSA register when
executed on a MIPS big endian CPU, didn't pick the
right element, and was behaving like on little endian.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
 target/mips/msa_helper.c | 7 +++++++
 1 file changed, 7 insertions(+)
diff mbox series

Patch

diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 8caf186..ac5d41e 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1500,6 +1500,13 @@  void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
 {
     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
     target_ulong rs = env->active_tc.gpr[rs_num];
+#if defined(HOST_WORDS_BIGENDIAN)
+    if (n < DF_ELEMENTS(df) / 2) {
+        n = DF_ELEMENTS(df) / 2 - n - 1;
+    } else {
+        n = 3 * DF_ELEMENTS(df) / 2 - n - 1;
+    }
+#endif
 
     switch (df) {
     case DF_BYTE: