diff mbox series

[v2,5/7] target/mips: Eliminate unreachable case for MSA instructions copy_u

Message ID 1553525566-14913-6-git-send-email-mateja.marjanovic@rt-rk.com (mailing list archive)
State New, archived
Headers show
Series target/mips: Add support for MSA instructions on a big endian host | expand

Commit Message

Mateja Marjanovic March 25, 2019, 2:52 p.m. UTC 
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>

The copy_u instruction doesn't support doublewords, and supports
words only if the CPU is MIPS64 [1] (page 138), for MIPS32 it
supports only byte and halfword [2] (page 138).

[1] MIPS Architecture for Programmers
    Volume IV-j: The MIPS64 SIMD
    Architecture Module
[2] MIPS Architecture for Programmers
    Volume IV-j: The MIPS32 SIMD
    Architecture Module

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
 target/mips/msa_helper.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

Comments

Aleksandar Markovic March 25, 2019, 9:16 p.m. UTC | #1 
> From: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
> Sent: Monday, March 25, 2019 3:52 PM
> To: qemu-devel@nongnu.org
> Cc: aurelien@aurel32.net; Aleksandar Markovic; Aleksandar Rikalo
> Subject: [PATCH v2 5/7] target/mips: Eliminate unreachable case for MSA instructions copy_u
> 
> From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
> 
> The copy_u instruction doesn't support doublewords, and supports
> words only if the CPU is MIPS64 [1] (page 138), for MIPS32 it
> supports only byte and halfword [2] (page 138).
>
> [1] MIPS Architecture for Programmers
>     Volume IV-j: The MIPS64 SIMD
>     Architecture Module
> [2] MIPS Architecture for Programmers
>     Volume IV-j: The MIPS32 SIMD
>     Architecture Module

It is not enough to cite the document title, you need release number.
The latest for both MSA docs are I think 6.12. Download them from
official MIPS site, and check the page numbers again.

This patch should be split into two: one if "ifdef-ing" "W" case, and
another for deleting "D" case.

Thanks,
Aleksandar
Mateja Marjanovic March 26, 2019, 6:37 a.m. UTC | #2 
On 25.3.19. 22:16, Aleksandar Markovic wrote:
>> From: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
>> Sent: Monday, March 25, 2019 3:52 PM
>> To: qemu-devel@nongnu.org
>> Cc: aurelien@aurel32.net; Aleksandar Markovic; Aleksandar Rikalo
>> Subject: [PATCH v2 5/7] target/mips: Eliminate unreachable case for MSA instructions copy_u
>>
>> From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
>>
>> The copy_u instruction doesn't support doublewords, and supports
>> words only if the CPU is MIPS64 [1] (page 138), for MIPS32 it
>> supports only byte and halfword [2] (page 138).
>>
>> [1] MIPS Architecture for Programmers
>>      Volume IV-j: The MIPS64 SIMD
>>      Architecture Module
>> [2] MIPS Architecture for Programmers
>>      Volume IV-j: The MIPS32 SIMD
>>      Architecture Module
> It is not enough to cite the document title, you need release number.
> The latest for both MSA docs are I think 6.12. Download them from
> official MIPS site, and check the page numbers again.
I will correct that in v3.
>
> This patch should be split into two: one if "ifdef-ing" "W" case, and
> another for deleting "D" case.
Same goes for this.
>
> Thanks,
> Aleksandar
Regards,
Mateja
diff mbox series

Patch

diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index ac5d41e..f368f79 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1482,13 +1482,10 @@  void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
     case DF_HALF:
         env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
         break;
+#ifdef TARGET_MIPS64
     case DF_WORD:
         env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
         break;
-#ifdef TARGET_MIPS64
-    case DF_DOUBLE:
-        env->active_tc.gpr[rd] = (uint64_t)env->active_fpu.fpr[ws].wr.d[n];
-        break;
 #endif
     default:
         assert(0);