| Message ID | 1565020823-24223-10-git-send-email-bmeng.cn@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: sifive_u: Improve the emulation fidelity of sifive_u machine | expand |
Reviewed-by: Jonathan Behrens <fintelia@gmail.com> <chihmin.chao@sifive.com> On Mon, Aug 5, 2019 at 12:07 PM Bin Meng <bmeng.cn@gmail.com> wrote: > This updates the UART base address to match the hardware. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > --- > > hw/riscv/sifive_u.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index b235f29..9f05e09 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -60,8 +60,8 @@ static const struct MemmapEntry { > [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, > [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, > [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, > - [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, > - [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, > + [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, > + [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, > [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, > [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, > }; > -- > 2.7.4 > > >
On Mon, Aug 5, 2019 at 9:05 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > This updates the UART base address to match the hardware. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > hw/riscv/sifive_u.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index b235f29..9f05e09 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -60,8 +60,8 @@ static const struct MemmapEntry { > [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, > [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, > [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, > - [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, > - [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, > + [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, > + [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, > [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, > [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, > }; > -- > 2.7.4 > >
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index b235f29..9f05e09 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -60,8 +60,8 @@ static const struct MemmapEntry { [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, - [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, - [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, + [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, + [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, };
This updates the UART base address to match the hardware. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- hw/riscv/sifive_u.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)