| Message ID | 1565163924-18621-4-git-send-email-bmeng.cn@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: sifive_u: Improve the emulation fidelity of sifive_u machine | expand |
On 8/7/19 9:44 AM, Bin Meng wrote: > Group SiFive E and U cpu type defines into one header file. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > --- > > Changes in v2: None > > include/hw/riscv/sifive_cpu.h | 31 +++++++++++++++++++++++++++++++ > include/hw/riscv/sifive_e.h | 7 +------ > include/hw/riscv/sifive_u.h | 7 +------ > 3 files changed, 33 insertions(+), 12 deletions(-) > create mode 100644 include/hw/riscv/sifive_cpu.h > > diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h > new file mode 100644 > index 0000000..1367996 > --- /dev/null > +++ b/include/hw/riscv/sifive_cpu.h > @@ -0,0 +1,31 @@ > +/* > + * SiFive CPU types > + * > + * Copyright (c) 2017 SiFive, Inc. > + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#ifndef HW_SIFIVE_CPU_H > +#define HW_SIFIVE_CPU_H > + > +#if defined(TARGET_RISCV32) > +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 > +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 > +#elif defined(TARGET_RISCV64) > +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 > +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 > +#endif > + > +#endif /* HW_SIFIVE_CPU_H */ > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h > index d175b24..e17cdfd 100644 > --- a/include/hw/riscv/sifive_e.h > +++ b/include/hw/riscv/sifive_e.h > @@ -19,6 +19,7 @@ > #ifndef HW_SIFIVE_E_H > #define HW_SIFIVE_E_H > > +#include "hw/riscv/sifive_cpu.h" > #include "hw/riscv/sifive_gpio.h" > > #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc" > @@ -83,10 +84,4 @@ enum { > #define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000 > #define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000 > > -#if defined(TARGET_RISCV32) > -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 > -#elif defined(TARGET_RISCV64) > -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 > -#endif > - > #endif > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h > index 892f0ee..4abc621 100644 > --- a/include/hw/riscv/sifive_u.h > +++ b/include/hw/riscv/sifive_u.h > @@ -20,6 +20,7 @@ > #define HW_SIFIVE_U_H > > #include "hw/net/cadence_gem.h" > +#include "hw/riscv/sifive_cpu.h" > > #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" > #define RISCV_U_SOC(obj) \ > @@ -77,10 +78,4 @@ enum { > #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 > #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 > > -#if defined(TARGET_RISCV32) > -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 > -#elif defined(TARGET_RISCV64) > -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 > -#endif > - > #endif >
diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h new file mode 100644 index 0000000..1367996 --- /dev/null +++ b/include/hw/riscv/sifive_cpu.h @@ -0,0 +1,31 @@ +/* + * SiFive CPU types + * + * Copyright (c) 2017 SiFive, Inc. + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_SIFIVE_CPU_H +#define HW_SIFIVE_CPU_H + +#if defined(TARGET_RISCV32) +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 +#elif defined(TARGET_RISCV64) +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 +#endif + +#endif /* HW_SIFIVE_CPU_H */ diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index d175b24..e17cdfd 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -19,6 +19,7 @@ #ifndef HW_SIFIVE_E_H #define HW_SIFIVE_E_H +#include "hw/riscv/sifive_cpu.h" #include "hw/riscv/sifive_gpio.h" #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc" @@ -83,10 +84,4 @@ enum { #define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000 #define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000 -#if defined(TARGET_RISCV32) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 -#elif defined(TARGET_RISCV64) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 -#endif - #endif diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 892f0ee..4abc621 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -20,6 +20,7 @@ #define HW_SIFIVE_U_H #include "hw/net/cadence_gem.h" +#include "hw/riscv/sifive_cpu.h" #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" #define RISCV_U_SOC(obj) \ @@ -77,10 +78,4 @@ enum { #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 -#if defined(TARGET_RISCV32) -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 -#elif defined(TARGET_RISCV64) -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 -#endif - #endif