[v5,07/30] riscv: roms: Remove executable attribute of opensbi images

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From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
 Palmer Dabbelt <palmer@sifive.com>, qemu-devel@nongnu.org,
 qemu-riscv@nongnu.org
Date: Thu, 22 Aug 2019 22:10:46 -0700
Message-Id: <1566537069-22741-8-git-send-email-bmeng.cn@gmail.com>
In-Reply-To: <1566537069-22741-1-git-send-email-bmeng.cn@gmail.com>
References: <1566537069-22741-1-git-send-email-bmeng.cn@gmail.com>
Subject: [Qemu-devel] [PATCH v5 07/30] riscv: roms: Remove executable
 attribute of opensbi images
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 qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org
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 <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>

Message ID	1566537069-22741-8-git-send-email-bmeng.cn@gmail.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=emGm=WT=nongnu.org=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 666772070B From: Bin Meng <bmeng.cn@gmail.com> To: Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Thu, 22 Aug 2019 22:10:46 -0700 Message-Id: <1566537069-22741-8-git-send-email-bmeng.cn@gmail.com> In-Reply-To: <1566537069-22741-1-git-send-email-bmeng.cn@gmail.com> References: <1566537069-22741-1-git-send-email-bmeng.cn@gmail.com> Subject: [Qemu-devel] [PATCH v5 07/30] riscv: roms: Remove executable attribute of opensbi images Precedence: list Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	riscv: sifive_u: Improve the emulation fidelity of sifive_u machine \| expand [v5,00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine [v5,01/30] riscv: hw: Remove superfluous "linux, phandle" property [v5,02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell [v5,03/30] riscv: hw: Remove not needed PLIC properties in device tree [v5,04/30] riscv: hw: Change create_fdt() to return void [v5,05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead [v5,06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h [v5,07/30] riscv: roms: Remove executable attribute of opensbi images [v5,08/30] riscv: sifive_u: Remove the unnecessary include of prci header [v5,09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} [v5,10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming [v5,11/30] riscv: sifive_e: prci: Update the PRCI register block size [v5,13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines [v5,14/30] riscv: hart: Extract hart realize to a separate routine [v5,15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array [v5,16/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC [v5,17/30] riscv: sifive_u: Set the minimum number of cpus to 2 [v5,18/30] riscv: sifive_u: Update PLIC hart topology configuration string [v5,19/30] riscv: sifive: Implement PRCI model for FU540 [v5,20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes [v5,21/30] riscv: sifive_u: Add PRCI block to the SoC [v5,22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes [v5,23/30] riscv: sifive_u: Update UART base addresses and IRQs [v5,24/30] riscv: sifive_u: Change UART node name in device tree [v5,25/30] riscv: roms: Update default bios for sifive_u machine [v5,26/30] riscv: sifive: Implement a model for SiFive FU540 OTP [v5,28/30] riscv: sifive_u: Fix broken GEM support [v5,29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet [v5,30/30] riscv: sifive_u: Update model and compatible strings in device tree

[v5,07/30] riscv: roms: Remove executable attribute of opensbi images

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Patch